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AD9518-3A-PCBZ PDF预览

AD9518-3A-PCBZ

更新时间: 2024-01-28 08:44:54
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
64页 1002K
描述
6-Output Clock Generator with 6-Output Clock Generator with

AD9518-3A-PCBZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC48,.27SQ,20针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.73
系列:9518输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm逻辑集成电路类型:CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:48实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:1.18 ns
传播延迟(tpd):1.18 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.22 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm
最小 fmax:2950 MHzBase Number Matches:1

AD9518-3A-PCBZ 数据手册

 浏览型号AD9518-3A-PCBZ的Datasheet PDF文件第3页浏览型号AD9518-3A-PCBZ的Datasheet PDF文件第4页浏览型号AD9518-3A-PCBZ的Datasheet PDF文件第5页浏览型号AD9518-3A-PCBZ的Datasheet PDF文件第7页浏览型号AD9518-3A-PCBZ的Datasheet PDF文件第8页浏览型号AD9518-3A-PCBZ的Datasheet PDF文件第9页 
AD9518-3  
Data Sheet  
CLOCK INPUTS  
Table 3.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
CLOCK INPUTS (CLK, CLK)  
Input Frequency  
Differential input  
01  
01  
2.4  
1.6  
GHz  
GHz  
High frequency distribution (VCO divider)  
Distribution only (VCO divider bypassed)  
Input Sensitivity, Differential  
Input Level, Differential  
150  
mV p-p Measured at 2.4 GHz; jitter performance is  
improved with slew rates > 1 V/ns  
2
V p-p  
Larger voltage swings may turn on the  
protection diodes and may degrade jitter  
performance  
Input Common-Mode Voltage, VCM  
Input Common-Mode Range, VCMR  
Input Sensitivity, Single-Ended  
Input Resistance  
1.3  
1.3  
1.57  
1.8  
1.8  
V
V
Self-biased; enables ac coupling  
With 200 mV p-p signal applied; dc-coupled  
150  
4.7  
2
mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground  
3.9  
5.7  
kΩ  
pF  
Self-biased  
Input Capacitance  
1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM  
.
CLOCK OUTPUTS  
Table 4.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
Termination = 50 Ω to VS − 2 V  
Differential (OUT, OUT)  
LVPECL CLOCK OUTPUTS  
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5  
Output Frequency, Maximum  
2950  
MHz  
V
Using direct to output; see Figure 16 for peak-  
to-peak differential amplitude  
VS_LVPECL  
1.12  
VS_LVPECL  
2.03  
VS_LVPECL  
0.98  
VS_LVPECL  
1.77  
VS_LVPECL  
0.84  
VS_LVPECL  
1.49  
Output High Voltage (VOH)  
Output Low Voltage (VOL)  
V
This is VOH − VOL for each leg of a differential pair  
for default amplitude setting with driver not  
toggling; the peak-to-peak amplitude measured  
using a differential probe across the differential  
pair with the driver toggling is roughly 2× these  
values (see Figure 16 for variation over frequency)  
Output Differential Voltage (VOD)  
550  
790  
980  
mV  
TIMING CHARACTERISTICS  
Table 5.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
LVPECL  
Output Rise Time, tRP  
Output Fall Time, tFP  
Termination = 50 Ω toVS − 2 V; level = 810 mV  
20ꢀ to 80ꢀ, measured differentially  
80ꢀ to 20ꢀ, measured differentially  
70  
70  
180  
180  
ps  
ps  
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL  
OUTPUT  
High Frequency Clock Distribution  
Configuration  
Clock Distribution Configuration  
835  
773  
995  
1180  
1090  
ps  
See Figure 28  
See Figure 30  
933  
0.8  
ps  
ps/°C  
Variation with Temperature  
OUTPUT SKEW, LVPECL OUTPUTS1  
LVPECL Outputs That Share the Same Divider  
LVPECL Outputs on Different Dividers  
All LVPECL Outputs Across Multiple Parts  
5
13  
15  
40  
220  
ps  
ps  
ps  
1 This is the difference between any two similar delay paths while operating at the same voltage and temperature.  
Rev. B | Page 6 of 64  
 
 
 
 

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