AD9516-3
TABLE OF CONTENTS
Features .............................................................................................. 1
Phase-Locked Loop (PLL) .................................................... 33
Configuration of the PLL...................................................... 33
Phase Frequency Detector (PFD) ........................................ 33
Charge Pump (CP)................................................................. 34
On-Chip VCO ........................................................................ 34
PLL External Loop Filter....................................................... 34
PLL Reference Inputs............................................................. 34
Reference Switchover............................................................. 35
Reference Divider R............................................................... 35
VCXO/VCO Feedback Divider N: P, A, B, R ..................... 35
Digital Lock Detect (DLD) ....................................................... 37
Analog Lock Detect (ALD)................................................... 37
Current Source Digital Lock Detect (DLD) ....................... 37
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs............................................................................... 6
Timing Characteristics ................................................................ 7
Clock Output Additive Phase Noise (Distribution Only; VCO
Divider Not Used) ........................................................................ 8
Clock Output Absolute Phase Noise (Internal VCO Used).... 9
CLK
External VCXO/VCO Clock Input (CLK/
)................ 37
Clock Output Absolute Time Jitter (Clock Generation Using
Internal VCO)............................................................................. 10
Holdover.................................................................................. 38
Manual Holdover Mode........................................................ 38
Automatic/Internal Holdover Mode.................................... 38
Frequency Status Monitors ................................................... 39
VCO Calibration .................................................................... 40
Clock Distribution ..................................................................... 41
Internal VCO or External CLK as Clock Source ............... 41
CLK or VCO Direct to LVPECL Outputs........................... 41
Clock Frequency Division..................................................... 42
VCO Divider........................................................................... 42
Channel Dividers—LVPECL Outputs................................. 42
Channel Dividers—LVDS/CMOS Outputs........................ 44
Synchronizing the Outputs—SYNC Function................... 47
Clock Outputs......................................................................... 49
LVPECL Outputs: OUT0 to OUT5 ..................................... 49
LVDS/CMOS Outputs: OUT6 to OUT9............................. 50
Reset Modes ................................................................................ 50
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO)............................................................................. 10
Clock Output Absolute Time Jitter (Clock Generation Using
External VCXO) ......................................................................... 10
Clock Output Additive Time Jitter (VCO Divider Not Used)....11
Clock Output Additive Time Jitter (VCO Divider Used) ..... 11
Delay Block Additive Time Jitter.............................................. 12
Serial Control Port ..................................................................... 12
,
, and
Pins ..................................................... 13
RESET
PD SYNC
LD, STATUS, REFMON Pins.................................................... 13
Power Dissipation....................................................................... 14
Timing Diagrams............................................................................ 15
Absolute Maximum Ratings.......................................................... 16
Thermal Resistance .................................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 19
Terminology .................................................................................... 25
Detailed Block Diagram ................................................................ 26
Theory of Operation ...................................................................... 27
Operational Configurations...................................................... 27
Power-On Reset—Start-Up Conditions When VS Is
Applied .................................................................................... 50
RESET
Asynchronous Reset via the
Pin ............................. 50
Soft Reset via 0x00<5> .......................................................... 50
Power-Down Modes .................................................................. 50
PD
Chip Power-Down via
.................................................... 50
High Frequency Clock Distribution—CLK or External
VCO >1600 MHz ................................................................... 27
PLL Power-Down................................................................... 51
Distribution Power-Down .................................................... 51
Individual Clock Output Power-Down............................... 51
Internal VCO and Clock Distribution................................. 29
Clock Distribution or External VCO <1600 MHz............. 31
Rev. 0 | Page 2 of 84
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