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AD9433BST-125 PDF预览

AD9433BST-125

更新时间： 2024-02-13 21:21:22
品牌 Logo 应用领域
亚德诺 - ADI 信息通信管理转换器
页数 文件大小 规格书
20页 393K
描述
IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, PLASTIC, LQFP-52, Analog to Digital Converter

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AD9433BST-125 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, LQFP-52
针数：52Reach Compliance Code：not_compliant
ECCN代码：3A991.C.2HTS代码：8542.39.00.01
风险等级：5.78最大模拟输入电压：1 V
最小模拟输入电压：-1 V转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-PQFP-G52JESD-609代码：e0
长度：10 mm最大线性误差 (EL)：0.0183%
模拟输入通道数量：1位数：12
功能数量：1端子数量：52
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式：PARALLEL, WORD
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP52,.47SQ封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3,5 V认证状态：Not Qualified
采样速率：125 MHz采样并保持/跟踪并保持：TRACK
座面最大高度：1.6 mm子类别：Analog to Digital Converters
标称供电电压：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
Base Number Matches：1

AD9433BST-125 数据手册

 浏览型号AD9433BST-125的Datasheet PDF文件第2页浏览型号AD9433BST-125的Datasheet PDF文件第3页浏览型号AD9433BST-125的Datasheet PDF文件第4页浏览型号AD9433BST-125的Datasheet PDF文件第5页浏览型号AD9433BST-125的Datasheet PDF文件第6页浏览型号AD9433BST-125的Datasheet PDF文件第7页 
12-Bit, 105 MSPS/125 MSPS,  
IF Sampling ADC  
AD9433  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
IF sampling up to 350 MHz  
V
V
DD  
CC  
AD9433  
SNR: 67.5 dB, fIN up to Nyquist at 105 MSPS  
SFDR: 83 dBc, fIN = 70 MHz at 105 MSPS  
SFDR: 72 dBc, fIN = 150 MHz at 105 MSPS  
2 V p-p analog input range  
On-chip clock duty cycle stabilization  
On-chip reference and track-and-hold  
SFDR optimization circuit  
AIN  
AIN  
12  
PIPELINE  
ADC  
T/H  
12  
OUTPUT  
STAGING  
D11 TO D0  
DFS  
ENCODE  
ENCODE  
ENCODE  
TIMING  
REF  
SFDR  
MODE  
GND  
VREFOUT VREFIN  
Excellent linearity  
Figure 1.  
DNL: 0.25 LSB (typical)  
INL: 0.5 LSB (typical)  
A user-selectable, on-chip proprietary circuit optimizes  
750 MHz full power analog bandwidth  
Power dissipation: 1.35 W (typical) at 125 MSPS  
Twos complement or offset binary data format  
5.0 V analog supply operation  
spurious-free dynamic range (SFDR) vs. signal-to-noise and  
distortion (SINAD) ratio performance for different input signal  
frequencies, providing as much as 83 dBc SFDR performance  
over the dc to 70 MHz band.  
2.5 V to 3.3 V TTL/CMOS outputs  
The encode clock supports either differential or single-ended  
input and is PECL-compatible. The output format is user-  
selectable for offset binary or twos complement and provides  
an overrange (OR) signal.  
APPLICATIONS  
Cellular infrastructure communication systems  
3G single- and multicarrier receivers  
IF sampling schemes  
Wideband carrier frequency systems  
Point-to-point radios  
LMDS, wireless broadband  
MMDS base station units  
Cable reverse path  
Fabricated on an advanced BiCMOS process, the AD9433 is  
available in a 52-lead thin quad flat package (TQFP_EP) that  
is specified over the industrial temperature range of −40°C to  
+85°C. The AD9433 is pin-compatible with the AD9432.  
PRODUCT HIGHLIGHTS  
Communications test equipment  
Radar and satellite ground systems  
1. IF Sampling.  
The AD9433 maintains outstanding ac performance up to  
input frequencies of 350 MHz. Suitable for 3G wideband  
cellular IF sampling receivers.  
GENERAL INTRODUCTION  
The AD9433 is a 12-bit, monolithic sampling analog-to-digital  
converter (ADC) with an on-chip track-and-hold circuit and is  
designed for ease of use. The product operates up to a 125 MSPS  
conversion rate and is optimized for outstanding dynamic per-  
formance in wideband and high IF carrier systems.  
2. Pin-Compatibility with the AD9432.  
The AD9433 has the same footprint and pin layout as the  
AD9432 12-bit 80 MSPS/105 MSPS ADC.  
3. SFDR Performance.  
A user-selectable, on-chip circuit optimizes SFDR  
performance as much as 83 dBc from dc to 70 MHz.  
4. Sampling Rate.  
The ADC requires a 5 V analog power supply and a differential  
encode clock for full performance operation. No external refer-  
ence or driver components are required for many applications.  
The digital outputs are TTL-/CMOS-compatible, and a separate  
output power supply pin supports interfacing with 3.3 V or  
2.5 V logic.  
At 125 MSPS, the AD9433 is ideally suited for wireless and  
wired broadband applications such as LMDS/MMDS and  
cable reverse path.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.  
 
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