AD8802/AD8804
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
20
19
18
17
20
19
18
17
16
15
14
13
12
11
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance θJA,
V
1
2
V
1
2
V
V
DD
REFH
REFH
O1
DD
O1
RS
O12
O11
O10
O9
3
3
O2
O3
O4
O5
O6
O12
O11
O2
O3
O4
O5
O6
4
4
5
16 O10
15 O9
14 O8
5
AD8804
TOP VIEW
(Not to Scale)
AD8802
TOP VIEW
(Not to Scale)
6
6
O8
7
7
O7
8
8
13
SDI
SHDN
CS
O7
SHDN
CS
9
9
12 SDI
CLK
V
10
10
GND
11 CLK
GND
REFL
SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
AD8804 PIN DESCRIPTIONS
Pin Name Description
AD8802 PIN DESCRIPTIONS
Pin Name
Description
1
2
3
4
5
6
7
8
VREFH Common High-Side DAC Reference Input
1
2
3
4
5
6
7
8
VREF
O1
O2
O3
O4
O5
O6
Common DAC Reference Input
DAC Output #1, addr = 00002
DAC Output #2, addr = 00012
DAC Output #3, addr = 00102
DAC Output #4, addr = 00112
DAC Output #5, addr = 01002
DAC Output #6, addr = 01012
O1
O2
O3
O4
O5
O6
DAC Output #1, addr = 00002
DAC Output #2, addr = 00012
DAC Output #3, addr = 00102
DAC Output #4, addr = 00112
DAC Output #5, addr = 01002
DAC Output #6, addr = 01012
SHDN Reference input current goes to zero DAC latch
settings maintained
9
CS
Chip Select Input, Active Low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded input the
target DAC register
SHDN Reference input current goes to zero. DAC
latch settings maintained
9
CS
Chip Select Input, Active Low. When CS
returns high, data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register
10 GND
11 VREFL
12 CLK
13 SDI
14 O7
15 O8
16 O9
17 O10
18 O11
19 O12
20 VDD
Ground
Common Low-Side DAC Reference Input
Serial Clock Input, Positive Edge Triggered
Serial Data Input
10 GND
11 CLK
12 SDI
13 O7
Ground
DAC Output #7, addr = 01102
DAC Output #8, addr = 01112
DAC Output #9, addr = 10002
DAC Output #10, addr = 10012
DAC Output #11, addr = 10102
DAC Output #12, addr = 10112
Positive power supply, specified for operation at
both +3 V and +5 V
Serial Clock Input, Positive Edge Triggered
Serial Data Input
DAC Output #7, addr = 01102
DAC Output #8, addr = 01112
DAC Output #9, addr = 10002
DAC Output #10, addr = 10012
DAC Output #11, addr = 10102
DAC Output #12, addr = 10112
14 O8
15 O9
16 O10
17 O11
18 O12
19 RS
ORDERING GUIDE
Temperature Package
Package
Asynchronous Preset to Midscale Output
Setting. Loads all DAC Registers with 80H
Model
FTN
Range Description Option
AD8802AN
AD8802AR
AD8802ARU RS
AD8804AN
AD8804AR
AD8804ARU REFL
RS
RS
–40°C/+85°C PDIP-20
–40°C/+85°C SOL-20
–40°C/+85°C TSSOP-20
–40°C/+85°C PDIP-20
–40°C/+85°C SOL-20
–40°C/+85°C TSSOP-20
N-20
R-20
RU-20
N-20
R-20
20 VDD
Positive Power Supply, Specified for Operation
at Both +3 V and +5 V
REFL
REFL
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
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