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AD8428BRZ-RL

更新时间: 2024-01-06 08:11:54
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 348K
描述
Low Noise, Low Gain Drift, G = 2000

AD8428BRZ-RL 技术参数

生命周期:Active包装说明:DIE,
Reach Compliance Code:compliant风险等级:5.76
放大器类型:INSTRUMENTATION AMPLIFIER最大平均偏置电流 (IIB):0.2 µA
标称带宽 (3dB):3.5 MHz最小共模抑制比:130 dB
最大输入失调电流 (IIO):0.05 µA最大输入失调电压:100 µV
JESD-30 代码:R-XUUC-N8长度:2.89 mm
负供电电压上限:-18 V标称负供电电压 (Vsup):-15 V
最大非线性:0.0005%功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:RECTANGULAR
封装形式:UNCASED CHIP座面最大高度:0.3048 mm
标称压摆率:50 V/us子类别:Instrumentation Amplifier
供电电压上限:18 V标称供电电压 (Vsup):15 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
标称电压增益:2000宽度:1.755 mm
Base Number Matches:1

AD8428BRZ-RL 数据手册

 浏览型号AD8428BRZ-RL的Datasheet PDF文件第4页浏览型号AD8428BRZ-RL的Datasheet PDF文件第5页浏览型号AD8428BRZ-RL的Datasheet PDF文件第6页浏览型号AD8428BRZ-RL的Datasheet PDF文件第8页浏览型号AD8428BRZ-RL的Datasheet PDF文件第9页浏览型号AD8428BRZ-RL的Datasheet PDF文件第10页 
Data Sheet  
AD8428  
TYPICAL PERFORMANCE CHARACTERISTICS  
VS = 15 V, VREF = 0 V, TA = 25°C, G = 2000, RL = 10 kΩ, unless otherwise noted.  
1600  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
POSITIVE INPUT I  
BIAS  
N = 5170  
MEAN = 2.12  
SD = 7.332  
1400  
1200  
1000  
800  
600  
400  
200  
0
NEGATIVE INPUT I  
BIAS  
N = 5171  
MEAN = –10.8  
SD = 6.67496  
N = 5171  
MEAN = –10.2  
SD = 6.52901  
–60  
–40  
–20  
0
20  
40  
60  
–60  
–40  
–20  
0
20  
40  
60  
I
(nA)  
V
(µV)  
BIAS  
OSI  
Figure 3. Typical Distribution of Input Offset Voltage, VS = 5 V  
Figure 6. Typical Distribution of Input Bias Current  
1600  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
N = 5171  
N = 5169  
1400  
MEAN = –0.53  
MEAN = –2.57  
SD = 1.41655  
SD = 7.31066  
1200  
1000  
800  
600  
400  
200  
0
–8  
–6  
–4  
–2  
0
2
4
6
8
–60  
–40  
–20  
0
20  
40  
60  
I
(nA)  
V
(µV)  
OS  
OSI  
Figure 7. Typical Distribution of Input Offset Current  
Figure 4. Typical Distribution of Input Offset Voltage, VS = 15 V  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
1600  
N = 5166  
N = 3487  
1400  
MEAN = 0.398  
MEAN = –53.9  
SD = 86.7774  
SD = 0.42707  
1200  
1000  
800  
600  
400  
200  
0
–3  
–2  
–1  
0
1
2
3
–600  
–400  
–200  
0
200  
400  
600  
V
DRIFT (µV/°C)  
GAIN ERROR (µV/V)  
OSI  
Figure 5. Typical Distribution of Input Offset Voltage Drift  
Figure 8. Typical Distribution of Gain Error, Gain = 2000,  
VS = 15 V, RL = 10 kΩ  
Rev. A | Page 7 of 20  
 

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