AD8400/AD8402/AD8403–SPECIFICATIONS
1 k⍀ VERSION
ELECTRICAL CHARACTERISTICS otherwise noted)
(VDD = +3 V ؎ 10% or + 5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C ≤ TA ≤ +85؇C unless
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistance3
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
R-DNL
R-INL
R
∆RAB/∆T
RW
RWB, VA = NC
RWB, VA = NC
TA = +25°C, Model: AD840XYY1
VAB = VDD, Wiper = No Connect
IW = 1 V/RAB
–5
–4
0.8
–1
+3
+4
1.5
LSB
LSB
kΩ
ppm/°C
Ω
±1.5
1.2
700
53
100
2
∆R/RO
CH 1 to 2, VAB = VDD, TA = +25°C
0.75
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
8
Bits
Integral Nonlinearity4
Differential Nonlinearity4
INL
DNL
DNL
–6
–4
–5
±2
–1.5
–2
25
–12
6
+6
+2
+5
LSB
LSB
LSB
ppm/°C
LSB
LSB
VDD = +5 V
VDD = +3 V, TA = +25°C
Code = 80H
Code = FFH
Code = 00H
Voltage Divider Temperature Coefficent ∆VW/∆T
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
–20
0
0
10
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
CW
IDD_SD
RW_SD
0
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
75
pF
pF
µA
Ω
120
0.01
50
Shutdown Supply Current7
Shutdown Wiper Resistance
5
100
VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V
DIGITAL INPUTS & OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VOH
VOL
IIL
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
RL = 1 kΩ to VDD
IOL = 1.6 mA, VDD = +5 V
VIN = 0 V or +5 V, VDD = +5 V
2.4
V
V
V
V
V
V
µA
pF
0.8
0.6
2.1
Output Logic High
Output Logic Low
Input Current
VDD–0.1
0.4
±1
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Supply Range
VDD Range
IDD
IDD
PDISS
PSS
2.7
5.5
5
4
V
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
VIH = VDD or VIL = 0 V
0.01
0.9
µA
mA
µW
VIH = 2.4 V or 0.8 V, VDD = +5.5 V
VIH = VDD or VIL = 0 V, VDD = +5.5 V
∆VDD = +5 V ± 10%
27.5
0.0035 0.008 %/%
PSS
∆VDD = +3 V ± 10%
0.05
0.13
%/%
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
BW_1K
THDW
tS
eNWB
CT
R = 1 kΩ
5,000
0.015
0.5
3
–65
kHz
%
µs
nV/√Hz
dB
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% Error Band
RWB = 500 Ω, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
V
W Settling Time
Resistor Noise Voltage
Crosstalk11
NOTES FOR 1 kΩ VERSION
1 Typicals represent average readings at +25°C and VDD = +5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit.
IW = 500 µA for VDD = +3 V and IW = 4 mA for VDD = +5 V for 1 kΩ version.
3 VAB = VDD, Wiper (VW) = No Connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All Dynamic Characteristics use VDD = +5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
REV. B
–4–