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AD8402ARZ50 PDF预览

AD8402ARZ50

更新时间: 2024-01-03 01:14:43
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计电阻器光电二极管PC
页数 文件大小 规格书
32页 610K
描述
1-/2-/4-Channel Digital Potentiometers

AD8402ARZ50 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknown风险等级:5.3
其他特性:IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY标称带宽:0.125 kHz
控制接口:3-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm湿度敏感等级:1
功能数量:2位置数:256
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:COMMERCIAL电阻定律:LINEAR
最大电阻器端电压:5.5 V最小电阻器端电压:
座面最大高度:1.75 mm标称供电电压:3 V
表面贴装:YES标称温度系数:500 ppm/ °C
温度等级:AUTOMOTIVE端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
标称总电阻:50000 Ω宽度:3.9 mm
Base Number Matches:1

AD8402ARZ50 数据手册

 浏览型号AD8402ARZ50的Datasheet PDF文件第2页浏览型号AD8402ARZ50的Datasheet PDF文件第3页浏览型号AD8402ARZ50的Datasheet PDF文件第4页浏览型号AD8402ARZ50的Datasheet PDF文件第6页浏览型号AD8402ARZ50的Datasheet PDF文件第7页浏览型号AD8402ARZ50的Datasheet PDF文件第8页 
AD8400/AD8402/AD8403  
Parameter  
DYNAMIC CHARACTERISTICS6, 10  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
Bandwidth −3 dB  
Total Harmonic Distortion  
VW Settling Time  
BW_10 K  
THDW  
tS  
R = 10 kΩ  
600  
0.003  
2
kHz  
%
μs  
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz  
VA = VDD, VB = 0 V, 1% error band  
Resistor Noise Voltage  
Crosstalk11  
eNWB  
CT  
RS  
WB = 5 kΩ, f = 1 kHz, = 0  
VA = VDD, VB = 0 V  
9
nVꢀ√Hz  
dB  
R
−65  
1 Typical represents average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.  
I
W = 50 μA for VDD = 3 V and IW = 400 μA for VDD = 5 V for the 10 kΩ versions.  
3 VAB = VDD, wiper (VW) = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DꢀA converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.  
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining  
resistor terminals are left open circuit.  
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.  
8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.  
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
10 All dynamic characteristics use VDD = 5 V.  
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.  
Rev. E | Page 5 of 32  

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