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AD8402ARZ50 PDF预览

AD8402ARZ50

更新时间: 2024-02-24 15:00:35
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计电阻器光电二极管PC
页数 文件大小 规格书
32页 610K
描述
1-/2-/4-Channel Digital Potentiometers

AD8402ARZ50 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknown风险等级:5.3
其他特性:IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY标称带宽:0.125 kHz
控制接口:3-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm湿度敏感等级:1
功能数量:2位置数:256
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:COMMERCIAL电阻定律:LINEAR
最大电阻器端电压:5.5 V最小电阻器端电压:
座面最大高度:1.75 mm标称供电电压:3 V
表面贴装:YES标称温度系数:500 ppm/ °C
温度等级:AUTOMOTIVE端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
标称总电阻:50000 Ω宽度:3.9 mm
Base Number Matches:1

AD8402ARZ50 数据手册

 浏览型号AD8402ARZ50的Datasheet PDF文件第1页浏览型号AD8402ARZ50的Datasheet PDF文件第2页浏览型号AD8402ARZ50的Datasheet PDF文件第4页浏览型号AD8402ARZ50的Datasheet PDF文件第5页浏览型号AD8402ARZ50的Datasheet PDF文件第6页浏览型号AD8402ARZ50的Datasheet PDF文件第7页 
AD8400/AD8402/AD8403  
GENERAL DESCRIPTION  
(continued from Page 1)  
Each VR has its own VR latch that holds its programmed  
resistance value. These VR latches are updated from an SPI-  
compatible, serial-to-parallel shift register that is loaded from  
a standard 3-wire, serial-input digital interface. Ten data bits  
make up the data-word clocked into the serial input register.  
The AD8400 is available in the SOIC-8 surface mount. The  
AD8402 is available in both surface-mount (SOIC-14) and  
14-lead PDIP packages, while the AD8403 is available in a  
narrow-body, 24-lead PDIP and a 24-lead, surface-mount  
package. The AD8402/AD8403 are also offered in the 1.1 mm  
thin TSSOP-14/TSSOP-24 packages for PCMCIA applications.  
All parts are guaranteed to operate over the extended industrial  
temperature range of −40°C to +125°C.  
The data-word is decoded where the first two bits determine  
the address of the VR latch to be loaded, and the last eight bits  
are the data. A serial data output pin at the opposite end of the  
serial register allows simple daisy chaining in multiple VR  
applications without additional external decoding logic.  
RS  
The reset ( ) pin forces the wiper to midscale by loading 80H  
SHDN  
into the VR latch. The  
pin forces the resistor to an end-  
to-end open-circuit condition on the A terminal and shorts the  
wiper to the B terminal, achieving a microwatt power shutdown  
SHDN  
state. When  
is returned to logic high, the previous latch  
settings put the wiper in the same resistance setting prior to  
shutdown. The digital interface is still active in shutdown so  
that code changes can be made that will produce new wiper  
positions when the device is taken out of shutdown.  
Rev. E | Page 3 of 32  

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