Datasheet > AD8389ACPZ

AD8389ACPZ

更新时间： 2024-02-28 05:01:02

品牌	Logo	应用领域
亚德诺 - ADI		商用集成电路
页数	文件大小	规格书
12页	345K
描述
Triple, 6-Channel LCD Timing Delay-Locked Loop

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技术参数
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AD8389ACPZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.68
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
表面贴装：	YES	温度等级：	OTHER
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	7 mm
Base Number Matches：	1

AD8389ACPZ 数据手册

AD8389

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVSS

MONITRI

MONITGI

MONITBI

AVDD

36 DXRO

PIN 1

INDICATOR

35 ENBX1RO

34 ENBX2RO

33 ENBX3RO

32 ENBX4RO

31 CLXRO

AD8389

AVSS

TOP VIEW

VCONTR

AVDD

30 DXGO

(Not to Scale)

29 ENBX1GO

28 ENBX2GO

27 ENBX3GO

26 ENBX4GO

25 CLXGO

48-LEAD LFCSP

7mm × 7mm

AVSS

VCONTG 10

VCONTB 11

AVSS 12

NC =

NO CONNECT

Figure 3. 48-Lead LFCSP, 7 mm × 7 mm Pin Configuration

Table 3. Pin Function Descriptions

Mnemonic

AVDD, DRVDD

AVSS, DRVSS

CLK

Function

Power Supply

Ground

Description

Power Supply.

Ground.

Clock Input. Active edge is the rising edge.

Clock

COMPEDGE

Edge Select

When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of

MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling

edge of MONITxI.

SLOW

Delay Select

When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the

rising edges of MONITI is maintained at 9/(f_CLK) + t₄. The delay is maintained at 26/(f_CLK) + t₄when

COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges

of DXI and the rising edges of MONITI is maintained at 15/(f_CLK) + t₄. The delay is maintained at

32/(f_CLK) + t₄with COMPEDGE = LOW.

DXI

CLXI

Reference Input

Input

LCD Timing Input from the Image Processor. Used as the input to all phase detectors.

LCD Timing Input from the Image Processor.

ENBX(1–4)I

MONITxI

Inputs

Feedback Inputs

LCD Timing Inputs from the Image Processor.

Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389

forms part of a closed loop, it maintains a constant delay between the DXI input and this

reference input pin.

DXxO

CLXxO

ENBX(1–4)xO

VCONTx

Delayed Outputs

Control Voltage

200 pF capacitors connected between these pins and the AVSS plane are required for proper

operation of the internal charge pump.

Rev. 0 | Page 5 of 12

1 2 3 456 7 8...12

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