Datasheet > AD8361_1

AD8361_1

更新时间： 2022-10-09 09:19:58

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	853K
描述
LF to 2.5 GHz TruPwr? Detector

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AD8361_1 数据手册

AD8361

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPOS

IREF

SREF

VRMS

FLTR

VRMS

COMM

FLTR

VPOS

RFIN

AD8361

TOP VIEW

(Not to Scale)

RFIN

TOP VIEW

(Not to Scale)

PWDN

COMM

PWDN

Figure 4. 8-Lead MSOP

Figure 5. 6-Lead SOT-23

Table 3. Pin Function Descriptions

Pin No.

MSOP

Pin No.

SOT-23 Mnemonic Description

N/A

VPOS

IREF

Supply Voltage Pin. Operational range 2.7 V to 5.5 V.

Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this

pin should be tied to VPOS. Do not ground this pin.

RFIN

Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance

is 225 Ω.

Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than

100 mV). When a logic high (greater than V_S− 0.5 V) is applied, the device is turned off and the supply

current goes to nearly zero (ground and internal reference mode less than 1 µA, supply reference

mode V_Sdivided by 100 kΩ).

PWDN

COMM

FLTR

Device Ground Pin.

By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is

lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals.

VRMS

SREF

Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load

>10 kΩ to ground.

Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS;

otherwise, it should be connected to COMM (ground).

N/A

Rev. C | Page 5 of 24

1 2 3 456 7 8...24

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