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AD8362ARUZ PDF预览

AD8362ARUZ

更新时间: 2024-01-29 09:12:54
品牌 Logo 应用领域
亚德诺 - ADI 模拟IC信号电路光电二极管
页数 文件大小 规格书
32页 1029K
描述
50 Hz to 3.8 GHz 65 dB TruPwr? Detector

AD8362ARUZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:0.66
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

AD8362ARUZ 数据手册

 浏览型号AD8362ARUZ的Datasheet PDF文件第2页浏览型号AD8362ARUZ的Datasheet PDF文件第3页浏览型号AD8362ARUZ的Datasheet PDF文件第4页浏览型号AD8362ARUZ的Datasheet PDF文件第5页浏览型号AD8362ARUZ的Datasheet PDF文件第6页浏览型号AD8362ARUZ的Datasheet PDF文件第7页 
50 Hz to 3.8 GHz  
65 dB TruPwrDetector  
AD8362  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
DECL  
CHPF  
Complete fully calibrated measurement/control system  
Accurate rms-to-dc conversion from 50 Hz to 3.8 GHz  
Input dynamic range of >65 dB: −52 dBm to +8 dBm in 50 Ω  
Waveform and modulation independent, such as  
GSM/CDMA/TDMA  
Linear-in-decibels output, scaled 50 mV/dB  
Law conformance error of 0.5 dB  
All functions temperature and supply stable  
Operates from 4.5 V to 5.5 V at 24 mA  
INHI  
2
x
CLPF  
VOUT  
ACOM  
INLO  
2
VTGT  
x
Power-down capability to 1.3 mW  
VSET  
VPOS  
APPLICATIONS  
AD8362  
BIAS  
VREF  
Power amplifier linearization/control loops  
Transmitter power controls  
Transmitter signal strength indication (TSSI)  
RF instrumentation  
COMM  
PWDN  
Figure 1.  
GENERAL DESCRIPTION  
The AD8362 is a true rms-responding power detector that has  
a 65 dB measurement range. It is intended for use in a variety of  
high frequency communication systems and in instrumentation  
requiring an accurate response to signal power. It is easy to use,  
requiring only a single supply of 5 V and a few capacitors. It can  
operate from arbitrarily low frequencies to over 3.8 GHz and  
can accept inputs that have rms values from 1 mV to at least  
1 V rms, with large crest factors, exceeding the requirements  
for accurate measurement of CDMA signals.  
amplifier, thus balancing the setpoint against the input power.  
Optionally, the voltage at VSET can be a replica of the RF signal’s  
amplitude modulation, in which case the overall effect is to  
remove the modulation component prior to detection and low-  
pass filtering. The corner frequency of the averaging filter can  
be lowered without limit by adding an external capacitor at the  
CLPF pin. The AD8362 can be used to determine the true power  
of a high frequency signal having a complex low frequency  
modulation envelope, or simply as a low frequency rms volt-  
meter. The high-pass corner generated by its offset-nulling  
loop can be lowered by a capacitor added on the CHPF pin.  
The input signal is applied to a resistive ladder attenuator that  
comprises the input stage of a variable gain amplifier (VGA).  
The 12 tap points are smoothly interpolated using a proprietary  
technique to provide a continuously variable attenuator, which  
is controlled by a voltage applied to the VSET pin. The resulting  
signal is applied to a high performance broadband amplifier. Its  
output is measured by an accurate square-law detector cell. The  
fluctuating output is then filtered and compared with the output  
of an identical squarer, whose input is a fixed dc voltage applied  
to the VTGT pin, usually the accurate reference of 1.25 V pro-  
vided at the VREF pin.  
Used as a power measurement device, VOUT is strapped to  
VSET. The output is then proportional to the logarithm of the  
rms value of the input. In other words, the reading is presented  
directly in decibels and is conveniently scaled 1 V per decade,  
or 50 mV/dB; other slopes are easily arranged. In controller  
modes, the voltage applied to VSET determines the power level  
required at the input to null the deviation from the setpoint.  
The output buffer can provide high load currents.  
The AD8362 has 1.3 mW power consumption when powered  
down by a logic high applied to the PWDN pin. It powers up  
within about 20 μs to its nominal operating current of 20 mA at  
25°C. The AD8362 is supplied in a 16-lead TSSOP for operation  
over the temperature range of −40°C to +85°C.  
The difference in the outputs of these squaring cells is integrated  
in a high gain error amplifier, generating a voltage at the VOUT  
pin with rail-to-rail capabilities. In a controller mode, this low  
noise output can be used to vary the gain of a host systems RF  
Rev. D  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.  
 
 

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