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AD8362ARU-REEL7 PDF预览

AD8362ARU-REEL7

更新时间: 2024-01-19 18:56:16
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
36页 699K
描述
50 Hz to 2.7 GHz 60 dB TruPwr⑩ Detector

AD8362ARU-REEL7 技术参数

Source Url Status Check Date:2013-05-01 14:56:26.011是否无铅: 含铅
是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:MO-153AB, TSSOP-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.93模拟集成电路 - 其他类型:ANALOG CIRCUIT
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm湿度敏感等级:1
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm

AD8362ARU-REEL7 数据手册

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50 Hz to 2.7 GHz  
60 dB TruPwr™ Detector  
AD8362  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
DECL  
CHPF  
Complete fully calibrated measurement/control system  
Accurate rms-to-dc conversion from 50 Hz to 2.7 GHz  
Input dynamic range of >60 dB: −52 dBm to +8 dBm in 50 Ω  
Waveform and modulation independent:  
(Such as GSM/CDMA/TDMA)  
INHI  
2
x
CLPF  
VOUT  
ACOM  
INLO  
Linear-in-decibels output, scaled 50 mV/dB  
Law conformance error of 0.5 dB  
All functions temperature and supply stable  
Operates from 4.5 V to 5.5 V at 24 mA from −40°C to +85°C  
Power-down capability to 1.3 mW  
2
V
TGT  
x
VSET  
VPOS  
AD8362  
APPLICATIONS  
Power amplifier linearization/control loops  
BIAS  
VREF  
Transmitter power control  
Transmitter signal strength indication (TSSI)  
RF instrumentation  
COMM  
PWDN  
Figure 1.  
GENERAL DESCRIPTION  
The AD8362 is a true rms-responding power detector that has a  
60 dB measurement range. It is intended for use in a variety of  
high frequency communication systems and in instrumentation  
requiring an accurate response to signal power. It is easy to use,  
requiring only a single supply of 5 V and a few capacitors. It can  
operate from arbitrarily low frequencies to over 2.7 GHz and  
can accept inputs that have rms values from 1 mV to at least  
1 V rms, with peak crest factors of up to 6, exceeding the  
requirements for accurate measurement of CDMA signals.  
the input power. Optionally, the voltage at VSET may be a  
replica of the RF signals amplitude modulation, in which case  
the overall effect is to remove the modulation component prior  
to detection and low-pass filtering. The corner frequency of the  
averaging filter may be lowered without limit by adding an  
external capacitor at the CLPF pin. The AD8362 can be used to  
determine the true power of a high frequency signal having a  
complex low frequency modulation envelope (or simply as a  
low frequency rms voltmeter). The high-pass corner generated  
by its offset-nulling loop can be lowered by a capacitor added  
on the CHPF pin.  
The input signal is applied to a resistive ladder attenuator  
that comprises the input stage of a variable gain amplifier.  
The 12 tap points are smoothly interpolated using a proprietary  
technique to provide a continuously variable attenuator, which  
is controlled by a voltage applied to the VSET pin. The resulting  
signal is applied to a high performance broadband amplifier. Its  
output is measured by an accurate square-law detector cell. The  
fluctuating output is then filtered and compared with the output  
of an identical squarer, whose input is a fixed dc voltage applied  
to the VTGT pin, usually the accurate reference of 1.25 V  
provided at the VREF pin.  
Used as a power measurement device, VOUT is strapped to  
VSET, and the output is then proportional to the logarithm of  
the rms value of the input; that is, the reading is presented  
directly in decibels and is conveniently scaled 1 V per decade,  
that is, 50 mV/dB; other slopes are easily arranged. In controller  
modes, the voltage applied to VSET determines the power level  
required at the input to null the deviation from the setpoint.  
The output buffer can provide high load currents.  
The AD8362 is powered down by a logic high applied to the  
PWDN pin, i.e., the consumption is reduced to about 1.3 mW. It  
powers up within about 20 µs to its nominal operating current  
of 20 mA at 25°C. The AD8362 is supplied in a 16-lead TSSOP  
package for operation over the industrial temperature range of  
−40°C to +85°C. An evaluation board is available.  
The difference in the outputs of these squaring cells is  
integrated in a high gain error amplifier, generating a voltage at  
the VOUT pin with rail-to-rail capabilities. In a controller  
mode, this low noise output can be used to vary the gain of a  
host system’s RF amplifier, thus balancing the set point against  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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