AD8324JRQZ-REEL7

更新时间： 2024-01-11 21:30:46

品牌	Logo	应用领域
亚德诺 - ADI		驱动器
页数	文件大小	规格书
16页	416K
描述
3.3 V Upstream Cable Line Driver

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AD8324JRQZ-REEL7 数据手册

AD8324

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

GND

20 19 18 17 16

GND

TXEN

RAMP

GND

RAMP

AD8324

OUT+

AD8324

TOP VIEW

(Not to Scale)

IN+

IN–

OUT+

OUT–

TOP VIEW

OUT–

IN+

(Not to Scale)

12 BYP

IN–

GND

DATEN

SDATA

CLK

BYP

GND

SLEEP

11 GND

NC = NO CONNECT

Figure 5. 20-Lead LFCSP

Figure 6. 20-Lead QSOP

Table 6. Pin Function Descriptions

Pin No. Pin No.

20-Lead 20-Lead

LFCSP QSOP

1, 2, 5, 9, 1, 3, 4, 7,

Mnemonic

Description

GND

Common External Ground Reference.

18, 19

17, 20

11, 20

2, 19

V_CC

V_IN+

Common Positive External Supply Voltage.

Noninverting Input. DC-biased to approximately V_CC/2. Should be ac-coupled with a 0.1 μF

capacitor.

V_IN–

DATEN

Inverting Input. DC-biased to approximately V_CC/2. Should be ac-coupled with a 0.1 μF capacitor.

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A

Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and

simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data

latch (holds the previous and simultaneously enables the register for serial data load).

SDATA

CLK

Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit

to the slave. This requires the input serial data-word to be valid at or before this clock transition.

SLEEP

Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 μA. A

Logic 0 powers down the part (high Z_OUTstate), and a Logic 1 powers up the part.

BYP

Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor).

Negative Output Signal. Must be biased to V_CC. See Figure 23.

Positive Output Signal. Must be biased to V_CC. See Figure 23.

External RAMP Capacitor (Optional).

V_OUT–

V_OUT+

RAMP

TXEN

Logic 0 disables forward transmission. Logic 1 enables forward transmission.

Rev. A | Page 6 of 16

1...3 4 567 8 9...16

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