AD8316–SPECIFICATIONS
(VPOS = 2.7 V, TA = 25ꢃC, 52.3 ꢀ on RFIN, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range1
To Meet All Specifications
1 dB Log Conformance, 0.1 GHz
0.1
2.5
–10
+3
24.5
–78
–65
GHz
dBV
dBm
mV/dB
dBV
Input Voltage Range
Equivalent dBm Range
Logarithmic Slope2, 3
Logarithmic Intercept2, 3
Equivalent dBm Level
–58.6
–45.6
20.5
–68
0.1 GHz
0.1 GHz
22.1
–74
–61
–55
dBm
RF INPUT INTERFACE
Input Resistance4
Pin RFIN
0.1 GHz
0.1 GHz
2.9
1.0
kΩ
pF
Input Capacitance4
OUTPUTS
Pins OUT1 and OUT2
Minimum Output Voltage
VSET ≤ 200 mV, ENBL High, RF Input ≤ –60 dBm
0.1
0.15
0.025
0.25
2.6
12
V
V
V
V
ENBL Low
RL > 800 Ω
2.7 V ≤ VPOS ≤ 5.5 V
Source
Maximum Output Voltage
General Limit
Output Current Drive
Output Buffer Noise
Output Noise
2.45
VPOS – 0.1
mA
nV/√Hz
nV/√Hz
25
100
RF Input = 2 GHz, 0 dBm,
CFLT = 220 pF, fNOISE = 400 kHz
0.2 V to 2.6 V Swing
Small Signal Bandwidth
Slew Rate
Full-Scale Response Time
30
20
50
MHz
V/µs
ns
10%–90%, 250 mV Step (VSET), Open Loop5
FLTR = Open; Refer to TPC 28
SETPOINT INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Input Resistance
Pin VSET
Corresponding to Central 50 dB
0.25
1.8
1.5
V
43.5
100
16
dB/V
kΩ
V/µs
Slew Rate
ENABLE INTERFACE
Logic Level to Enable Power
Input Current when Enable High
Logic Level to Disable Power
Enable Time
Pin ENBL
VPOS
0.8
V
µA
V
20
7
Time from ENBL High to VAPC within 1% of
Final Value, CFLT = 68 pF; Refer to TPC 20
Time from ENBL Low to VAPC within 1% of
Final Value, CFLT = 68 pF; Refer to TPC 20
Time from VPOS/ENBL Low to VAPC within
1% of Final Value, CFLT = 68 pF; Refer to TPC 25
Time from VPOS/ENBL High to VAPC within
1% of Final Value, CFLT = 68 pF; Refer to TPC 25
µs
Disable Time
3
µs
µs
µs
Power-On/Enable Time
Power-Off/Disable Time
3
4
BAND SELECT INTERFACE
Logic Level to Enable OUT1
Input Current when BSEL High
Logic Level to Enable OUT2
Pin BSEL
1.8
0.0
VPOS
1.7
V
µA
V
50
POWER INTERFACE
Supply Voltage
Quiescent Current
Over Temperature
Disable Current6
Over Temperature
Pin VPOS
2.7
5.5
10.7
12
10
13
V
ENBL High
–30°C ≤ TA ≤ +85°C
ENBL Low
8.5
3
mA
mA
µA
µA
–30°C ≤ TA ≤ +85°C
NOTES
1Operation down to 0.02 GHz is possible.
2Calculated over the input range of –40 dBm to –10 dBm.
3Mean and standard deviation specifications are in Table I.
4See TPC 9 for plot of Input Impedance vs. Frequency.
5Response time in a closed-loop system will depend upon the filter capacitor (CFLT) used and the response of the variable gain element.
6This parameter is guaranteed but not tested in production. The maximum specified limit on this parameter is the +6 sigma value from characterization.
Specifications subject to change without notice.
–2–
REV. C