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AD8304ARU-REEL7 PDF预览

AD8304ARU-REEL7

更新时间: 2024-01-27 10:59:13
品牌 Logo 应用领域
亚德诺 - ADI 转换器光电二极管放大器
页数 文件大小 规格书
20页 4103K
描述
160 dB Range (100 pA -10 mA) Logarithmic Converter

AD8304ARU-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:14
Reach Compliance Code:unknown风险等级:5.78
模拟集成电路 - 其他类型:LOG OR ANTILOG AMPLIFIER标称带宽:10 MHz
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:5 mm湿度敏感等级:1
负电源电压最大值(Vsup):-5.5 V功能数量:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
认证状态:COMMERCIAL座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

AD8304ARU-REEL7 数据手册

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160 dB Range (100 pA –10 mA)  
Logarithmic Converter  
a
AD8304  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Optimized for Fiber Optic Photodiode Interfacing  
Eight Full Decades of Range  
VPS2  
10  
PWDN  
2
VPS1  
12  
Law Conformance 0.1 dB from 1 nA to 1 mA  
Single-Supply Operation (3.0 V– 5.5 V)  
Complete and Temperature Stable  
AD8304  
PDB  
BIAS  
VREF  
7
8
VREF  
VLOG  
VPDB  
6
Accurate Laser-Trimmed Scaling:  
~10k  
0.5V  
VSUM  
INPT  
Logarithmic Slope of 10 mV/dB (at VLOG Pin)  
Basic Logarithmic Intercept at 100 pA  
Easy Adjustment of Slope and Intercept  
Output Bandwidth of 10 MHz, 15 V/s Slew Rate  
1-, 2-, or 3-Pole Low-Pass Filtering at Output  
Miniature 14-Lead Package (TSSOP)  
Low Power: ~4.5 mA Quiescent Current (Enabled)  
3
4
I
PD  
9
BFIN  
5k⍀  
TEMPERATURE  
COMPENSATION  
5
VSUM  
BFNG  
13  
1
14  
11  
APPLICATIONS  
VNEG  
ACOM  
VOUT  
High Accuracy Optical Power Measurement  
Wide Range Baseband Log Compression  
Versatile Detector for APC Loops  
PRODUCT DESCRIPTION  
The default value of the logarithmic slope at the output VLOG is  
accurately scaled to 10 mV/dB (200 mV/decade). The resistance  
at this output is laser-trimmed to 5 k, allowing the slope to be  
lowered by shunting it with an external resistance; the addition  
of a capacitor at this pin provides a simple low-pass filter. The  
intermediate voltage VLOG is buffered in an output stage that can  
swing to within about 100 mV of ground (or VN) and the posi-  
tive supply, VP, and provides a peak current drive capacity of  
20 mA. The slope can be increased using the buffer and a pair  
of external feedback resistors. An accurate voltage reference of  
2 V is also provided to facilitate the repositioning of the intercept.  
The AD8304 is a monolithic logarithmic detector optimized for  
the measurement of low frequency signal power in fiber optic  
systems. It uses an advanced translinear technique to provide an  
exceptionally large dynamic range in a versatile and easily used  
form. Its wide measurement range and accuracy are achieved  
using proprietary design techniques and precise laser trimming.  
In most applications only a single positive supply, VP, of 5 V  
will be required, but 3.0 V to 5.5 V can be used, and certain  
applications benefit from the added use of a negative supply,  
VN. When using low supply voltages, the log slope is readily  
altered to fit the available span. The low quiescent current and  
chip disable features facilitate use in battery-operated applications.  
Many operational modes are possible. For example, low-pass filters  
of up to three poles may be implemented, to reduce the output  
noise at low input currents. The buffer may also serve as a com-  
parator, with or without hysteresis, using the 2 V reference, for  
example, in alarm applications. The incremental bandwidth of  
a translinear logarithmic amplifier inherently diminishes for small  
input currents. At the 1 nA level, the AD8304s bandwidth is  
about 2 kHz, but this increases in proportion to IPD up to a  
maximum value of 10 MHz.  
The input current, IPD, flows in the collector of an optimally  
scaled NPN transistor, connected in a feedback path around a  
low offset JFET amplifier. The current-summing input node  
operates at a constant voltage, independent of current, with a  
default value of 0.5 V; this may be adjusted over a wide range,  
including ground or below, using an optional negative supply.  
An adaptive biasing scheme is provided for reducing the dark  
current at very low light input levels. The voltage at Pin VPDB  
applies approximately 0.1 V across the diode for IPD = 100 pA,  
rising linearly with current to 2.0 V of net bias at IPD = 10 mA.  
The input pin INPT is flanked by the guard pins VSUM that  
track the voltage at the summing node to minimize leakage.  
The AD8304 is available in a 14-lead TSSOP package and specified  
for operation from 40°C to +85°C.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  

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