Datasheet > AD8300AN

AD8300AN

更新时间： 2024-02-23 02:29:27

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		输入元件光电二极管转换器
页数	文件大小	规格书
9页	927K
描述
SERIAL INPUT LOADING, 14us SETTLING TIME, 12-BIT DAC, PDIP8, PLASTIC, DIP-8

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AD8300AN 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	PLASTIC, DIP-8	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.82
Is Samacsys：	N	转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	SERIAL
JESD-30 代码：	R-PDIP-T8	JESD-609代码：	e0
长度：	9.88 mm	湿度敏感等级：	NOT SPECIFIED
位数：	12	功能数量：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	COMMERCIAL	座面最大高度：	5.33 mm
标称安定时间 (tstl)：	14 µs	标称供电电压：	3 V
表面贴装：	NO	技术：	BIPOLAR
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

AD8300AN 数据手册

AD8300

Table II. Unipolar Code Table

V_OHand V_OLvoltage levels. Consequently, for optimum dissipa-

tion use of CMOS logic versus TTL provides minimal dissipa-

tion in the static state. A V_INL= 0 V on the logic input pins

provides the lowest standby dissipation of 1.2 mA with a +3.3 V

power supply.

Hexadecimal

Number in

DAC Register

Decimal

Number in

DAC Register

Analog Output

Voltage (V)

FFF

801

800

7FF

000

4095

2049

2048

2047

+2.0475

+1.0245

+1.0240

+1.0235

+0.0000

As with any analog system, it is recommended that the AD8300

power supply be bypassed on the same PC card that contains

the chip. Figure 8 shows the power supply rejection versus fre-

quency performance. This should be taken into account when

using higher frequency switched-mode power supplies with

ripple frequencies of 100 kHz and higher.

One advantage of the rail-to-rail output amplifiers used in the

AD8300 is the wide range of usable supply voltage. The part is

fully specified and tested over temperature for operation from

+2.7 V to +5.5 V. If reduced linearity and source current capa-

bility near full scale can be tolerated, operation of the AD8300

is possible down to +2.1 volts. The minimum operating supply

voltage versus load current plot in Figure 2 provides information

for operation below V_DD= +2.7 V.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SOIC (SO-8)

0.1968 (5.00)

0.1890 (4.80)

TIMING AND CONTROL

The AD8300 has a separate serial-input register from the 12-bit

DAC register that allows preloading of a new data value MSB

first into the serial register without disturbing the present DAC

output voltage value. Data can only be loaded when the CS pin

is active low. After the new value is fully loaded in the serial-

input register, it can be asynchronously transferred to the DAC

sensitive LD strobe that should be returned high before any new

data is loaded into the serial-input register. At any time the

contents of the DAC resister can be reset to zero by strobing the

CLR pin which causes the DAC output voltage to go to zero

volts. All of the timing requirements are detailed in Figure 3

along with Table I. Control Logic Truth Table.

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

BSC

45؇

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0040 (0.10)

8؇

0؇

0.0500 (1.27)

0.0160 (0.41)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

SEATING

PLANE

8-Lead Plastic DIP (N-8)

0.430 (10.92)

0.348 (8.84)

All digital inputs are protected with a Zener type ESD protection

structure (Figure 22) that allows logic input voltages to exceed

the V_DDsupply voltage. This feature can be useful if the user is

loading one or more of the digital inputs with a 5 V CMOS logic

input voltage level while operating the AD8300 on a +3.3 V

power supply. If this mode of interface is used, make sure that

the V_OLof the +5 V CMOS meets the V_ILinput requirement of

the AD8300 operating at 3 V. See Figure 5 for the effect on

digital logic input threshold versus operating V_DDsupply voltage.

0.280 (7.11)

0.240 (6.10)

0.325 (8.25)

0.300 (7.62)

PIN 1

0.100 (2.54)

BSC

0.015

(0.381)

TYP

0.210

(5.33)

MAX

0.195 (4.95)

0.115 (2.93)

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.022 (0.558) 0.070 (1.77) SEATING

0.014 (0.356) 0.045 (1.15)

15؇

0؇

PLANE

LOGIC

GND

Figure 22. Equivalent Digital Input ESD Protection

Unipolar Output Operation

This is the basic mode of operation for the AD8300. The

AD8300 has been designed to drive loads as low as 400 Ω in

parallel with 500 pF. The code table for this operation is shown

in Table II.

APPLICATIONS INFORMATION

See DAC8512 data sheet for additional application circuit ideas.

–8–

REV. A

1...6 7 89

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与AD8300AN相关器件

型号	品牌	描述	获取价格	数据表
AD8300ANZ	ROCHESTER	SERIAL INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDIP8, PLASTIC, DIP-8	获取价格
AD8300AR	ADI	+3 Volt, Serial Input Complete 12-Bit DAC	获取价格
AD8300AR	ROCHESTER	SERIAL INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDSO8, 1.50 MM HEIGHT, LOW PROFILE,	获取价格
AD8300AR-REEL	ADI	暂无描述	获取价格
AD8300ARZ-REEL	ROCHESTER	SERIAL INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDSO8, 1.50 MM HEIGHT, LOW PROFILE,	获取价格
AD8302	ADI	LF.2.7 GHz RF/IF Gain and Phase Detector	获取价格

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