(V = VMIN to VMAX, TA = TMIN to TMAX ( unless otherwise noted)
AD805–SPECIFICATIONS
EE
AD805BN
Parameter
Condition
Min
Typ
Max
Units
NOMINAL DATA RATE1
155.52
Mbps
TRACKING RANGE/CAPTURE RANGE1
STATIC PHASE ERROR1
±50
±70
ppm of Nominal Data Rate
27–1 PRN Sequence
223–1 PRN Sequence
7
7
33
33
Degrees
Degrees
OUTPUT JITTER1
27–1 PRN Sequence
0.6
0.6
1.0
1.0
Degrees rms
Degrees rms
223–1 PRN Sequence
JITTER TOLERANCE1
f = 10 Hz
f = 30 Hz
f = 300 Hz
f = 6.5 kHz
f = 65 kHz
f = 650 kHz
f = 1.3 MHz
375
125
12.5
2.2
2.2
0.84
0.65
440
147
16
3.2
3.0
1.4
0.85
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
Unit Intervals p-p
JITTER TRANSFER1
Peaking
Bandwidth
27–1 PRN Sequence
0
10
0.12
1.1
dB
kHz
RECOVERED CLOCK SKEW
TRANSITIONLESS DATA RUN1
ACQUISITION TIME
TRCS
0.2
0.6
ns
1000 500
Bit Periods
Bit Periods
27–1 PRN Sequence
30
44
VCXO CONTROL OUTPUT RESISTANCE
VCXO Control Voltage High Level (VCC – VOH
VCXO Control Voltage Low Level (VOL – VEE
1000
1
0.8
Ω
Volts
Volts
)
No Load
No Load
1.3
1.15
)
POWER SUPPLY
Voltage (VMIN to VMAX
Current
)
–4.5
–5.2
70
–5.5
90
95
Volts
mA
mA
TA = +25°C, VEE = –5.2 V
TA = +25°C
INPUT VOLTAGE LEVELS
Input Logic High, VIH
Input Logic Low, VIL
–1.08
–1.95
–0.72 Volts
–1.59 Volts
OUTPUT VOLTAGE LEVELS
Output Logic High, VOH
Output Logic Low, VOL
TA = +25°C
TA = +25°C
–1.08
–1.95
–0.72 Volts
–1.60 Volts
INPUT CURRENT LEVELS
Input Logic High, IIH
Input Logic Low, IIL
125
80
µA
µA
OUTPUT SLEW TIMES
Rise Time (tR)
Fall Time (tF)
TA = +25°C
20%–80%
80%–20%
0.75
0.75
1.5
1.5
ns
ns
BUFFERED CLOCK DISTORTION
(DUTY CYCLE DISTORTION)
Recovered Clock Output
ρ = 1/2, TA = +25°C,
VEE = –5.2 V
±0.5
%
OPERATING TEMPERATURE RANGE1
(TMIN to TMAX
)
–40
+85
°C
VCXO CIRCUIT SPECIFICATIONS
Parameter
Condition
Min
Typ
Max
Units
CENTER FREQUENCY
CONTROL VOLTAGE
155.52
MHz
–4
–1
Volts
VCXO TUNING RANGE
MODULATION BANDWIDTH
±50
100
±70
ppm of Center Frequency
500
kHz
N/A
TRANSFER FUNCTION
NOTES
Positive, Monotonic
1These specifications reflect the performance of the circuit shown in Figure 12. VCXO circuit parameters critical to overall circuit performance are listed above.
2This specification results from tests accurate to ±0.1 dB, and from statistical analysis of the test results distribution. The AD805-VCXO circuit has no jitter peaking.
Reference the discussion in the THEORY OF OPERATION section.
Specifications subject to change without notice.
REV. 0
–2–