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AD8055AR-REEL

更新时间： 2024-01-04 00:54:40
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
11页 208K
描述
Low Cost, 300 MHz Voltage Feedback Amplifiers

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AD8055AR-REEL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：5.62
放大器类型：OPERATIONAL AMPLIFIER最大平均偏置电流 (IIB)：1.2 µA
标称共模抑制比：82 dB最大输入失调电压：10000 µV
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
标称负供电电压 (Vsup)：-5 V功能数量：1
端子数量：8最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
标称压摆率：840 V/us子类别：Operational Amplifier
供电电压上限：13.2 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
Base Number Matches：1

AD8055AR-REEL 数据手册

 浏览型号AD8055AR-REEL的Datasheet PDF文件第5页浏览型号AD8055AR-REEL的Datasheet PDF文件第6页浏览型号AD8055AR-REEL的Datasheet PDF文件第7页浏览型号AD8055AR-REEL的Datasheet PDF文件第8页浏览型号AD8055AR-REEL的Datasheet PDF文件第9页浏览型号AD8055AR-REEL的Datasheet PDF文件第11页 
AD8055/AD8056  
Power Dissipation Limits  
5
4
402⍀  
With a 10 V supply (total VCC – VEE), the quiescent power dissi-  
pation of the AD8055 in the SOT-23-5 package is 65 mW,  
while the quiescent power dissipation of the AD8056 in the  
microSOIC is 120 mW. This translates into a 15.6°C rise above  
the ambient for the SOT-23-5 package and a 24°C rise for the  
microSOIC package.  
402⍀  
C
= 30pF  
L
3
CL  
100⍀  
VIN = 0dBm  
2
50⍀  
1
0
The power dissipated under heavy load conditions is approxi-  
mately equal to the supply voltage minus the output voltage,  
times the load current, plus the quiescent power computed above.  
This total power dissipation is then multiplied by the thermal  
resistance of the package to find the temperature rise, above  
ambient, of the part. The junction temperature should be kept  
below 150°C.  
C
= 20pF  
= 10pF  
L
–1  
–2  
–3  
–4  
–5  
C
L
C
= 0pF  
L
0.3  
1
10  
FREQUENCY – MHz  
100  
500  
The AD8055 in the SOT-23-5 package can dissipate 270 mW  
while the AD8056 in the microSOIC package can dissipate  
325 mW (at 85°C ambient) without exceeding the maximum  
die temperature. In the case of the AD8056, this is greater than  
1.5 V rms into 50 Ω, enough to accommodate a 4 V p-p sine-wave  
signal on both outputs simultaneously. But since each output of  
the AD8055 or AD8056 is capable of supplying as much as  
110 mA into a short circuit, a continuous short circuit condition  
will exceed the maximum safe junction temperature.  
Figure 36. Capacitive Load Drive  
In general, to minimize peaking or to ensure the stability for  
larger values of capacitive loads, a small series resistor, RS, can  
be added between the op amp output and the capacitor, CL. For  
the setup depicted in Figure 37, the relationship between RS and  
CL was empirically derived and is shown in Figure 38. RS was  
chosen to produce less than 1 dB of peaking in the frequency  
response. Note also that after a sharp rise RS quickly settles to  
about 25 Ω.  
Resistor Selection  
The following table is provided as a guide to resistor selection  
for maintaining gain flatness vs. frequency for various values of  
gain.  
402⍀  
+5V  
0.1␮F  
10␮F  
–3 dB  
Bandwidth  
(MHz)  
402⍀  
7
2
3
FET PROBE  
R
S
V
6
AD8055  
Gain  
RF (⍀)  
RI (⍀)  
OUT  
C
L
4
V
= 0dBm  
IN  
+1  
+2  
+5  
+10  
0
402  
1k  
—
300  
160  
45  
50⍀  
10␮F  
402  
249  
100  
0.1␮F  
–5V  
909  
20  
Figure 37. Setup for RS vs. CL  
Driving Capacitive Loads  
40  
35  
30  
25  
20  
15  
10  
5
When driving a capacitive load, most op amps will exhibit peak-  
ing in the frequency response just before the frequency rolls off.  
Figure 36 shows the responses for an AD8056 running at a gain  
of +2, with a 100 Ω load that is shunted by various values of  
capacitance. It can be seen that under these conditions, the part  
is still stable with capacitive loads of up to 30 pF.  
0
0
10  
20  
30  
40  
– pF  
50  
60  
270  
C
L
Figure 38. RS vs. CL  
REV. B  
–10–  
1...7891011

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