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AD8027ART-REEL7 PDF预览

AD8027ART-REEL7

更新时间： 2024-02-02 03:44:04
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
24页 473K
描述
Low Distortion, High Speed Rail-to-Rail Input/Output Amplifiers

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AD8027ART-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOT-23, 6 PIN针数：6
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.33.00.01风险等级：8.09
放大器类型：OPERATIONAL AMPLIFIER架构：VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB)：11 µA标称带宽 (3dB)：190 MHz
最小共模抑制比：90 dB标称共模抑制比：110 dB
最大输入失调电流 (IIO)：0.9 µA最大输入失调电压：900 µV
JESD-30 代码：R-PDSO-G6JESD-609代码：e0
长度：2.9 mm低-失调：YES
湿度敏感等级：1负供电电压上限：-6.3 V
标称负供电电压 (Vsup)：-5 V功能数量：1
端子数量：6最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC
封装代码：LSSOP封装等效代码：SOP6,.11,38
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法：REEL功率：NO
可编程功率：NO座面最大高度：1.45 mm
标称压摆率：90 V/us供电电压上限：6.3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL最小电压增益：100
宽带：NO宽度：1.6 mm
Base Number Matches：1

AD8027ART-REEL7 数据手册

 浏览型号AD8027ART-REEL7的Datasheet PDF文件第3页浏览型号AD8027ART-REEL7的Datasheet PDF文件第4页浏览型号AD8027ART-REEL7的Datasheet PDF文件第5页浏览型号AD8027ART-REEL7的Datasheet PDF文件第7页浏览型号AD8027ART-REEL7的Datasheet PDF文件第8页浏览型号AD8027ART-REEL7的Datasheet PDF文件第9页 
AD8027/AD8028  
ABSOLUTE MAXIMUM RATINGS  
Table 4.  
PD = Quiescent Power +  
(
Total Drive Power – LoadPower  
)
Parameter  
Rating  
2
VS VOUT  
VOUT  
RL  
Supply Voltage  
12.6 V  
PD =  
(
VS × IS  
)
+
×
–
Power Dissipation  
See Figure 3  
VS 0.5 V  
1.8 V  
2
RL  
Common-Mode Input Voltage  
Differential Input Voltage  
Storage Temperature  
Operating Temperature Range  
RMS output voltages should be considered. If RL is referenced  
to VS–, as in single-supply operation, then the total drive power  
–65°C to +125°C  
–40°C to +125°C  
300°C  
is VS × IOUT  
.
Lead Temperature Range  
(Soldering 10 sec)  
If the rms signal levels are indeterminate, then consider the  
worst case, when VOUT = VS/4 for RL to midsupply  
Junction Temperature  
150°C  
2
(
VS/4  
RL  
)
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress rat-  
ing only; functional operation of the device at these or any  
other conditions above those indicated in the operational sec-  
tion of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
PD  
= VS ×IS +  
( )  
In single-supply operation with RL referenced to VS–, worst case  
is VOUT = VS/2.  
Airflow will increase heat dissipation, effectively reducing θJA.  
Also, more metal directly in contact with the package leads  
from metal traces, through holes, ground, and power planes will  
reduce the θJA. Care must be taken to minimize parasitic capaci-  
tances at the input leads of high speed op amps as discussed in  
the board layout section.  
Maximum Power Dissipation  
The maximum safe power dissipation in the AD8027/AD8028  
package is limited by the associated rise in junction temperature  
(TJ) on the die. The plastic encapsulating the die will locally  
reach the junction temperature. At approximately 150°C, which  
is the glass transition temperature, the plastic will change its  
properties. Even temporarily exceeding this temperature limit  
may change the stresses that the package exerts on the die,  
permanently shifting the parametric performance of the  
AD8027/AD8028. Exceeding a junction temperature of 175°C  
for an extended period of time can result in changes in the  
silicon devices, potentially causing failure.  
Figure 3 shows the maximum safe power dissipation in the  
package versus the ambient temperature for the SOIC-8  
(125°C/W), SOT-23-6 (170°C/W), and MSOP-10 (130°C/W)  
packages on a JEDEC standard 4-layer board.  
OUTPUT SHORT CIRCUIT  
Shorting the output to ground or drawing excessive current  
from the AD8027/AD8028 will likely cause catastrophic failure.  
2.0  
The still-air thermal properties of the package and PCB (θJA),  
ambient temperature (TA), and the total power dissipated in the  
package (PD) determine the junction temperature of the die.  
The junction temperature can be calculated as  
1.5  
SOIC-8  
TJ = TA +  
(
PD ×θJA  
)
1.0  
The power dissipated in the package (PD) is the sum of the  
quiescent power dissipation and the power dissipated in the  
package due to the load drive for all outputs. The quiescent  
power is the voltage between the supply pins (VS) times the  
quiescent current (IS). Assuming the load (RL) is referenced to  
midsupply, then the total drive power is VS/2 × IOUT, some of  
which is dissipated in the package and some in the load (VOUT  
MSOP-10  
SOT-23-6  
0.5  
0
–55  
–35  
–15  
5
25  
45  
65  
85  
105  
125  
×
AMBIENT TEMPERATURE (°C)  
03327-A-002  
IOUT). The difference between the total drive power and the load  
power is the drive power dissipated in the package.  
Figure 3. Maximum Power Dissipation  
Rev. B | Page 6 of 24  
1...3456789...24

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