AD800/AD802
T he PLL must provide a clock signal which tracks this phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation which tracks
the input jitter, some modulation signal must be generated at
the output of the phase detector (see Figure 21). T he
modulation output from the phase detector can only be
produced by a phase error between the data input and the clock
input. Hence, the PLL can never perfectly track jittered data.
However, the magnitude of the phase error depends on the gain
around the loop. At low frequencies the integrator provides very
high gain, and thus very large jitter can be tracked with small
phase errors between input data and recovered clock. At
frequencies closer to the loop bandwidth, the gain of the
integrator is much smaller, and thus less input jitter can be
tolerated. T he PLL data output will have a bit error rate less
than 1 ϫ 10–10 when in lock and retiming input data that has the
specified jitter applied to it.
Sym m etr y
Symmetry is calculated as (100 ϫ on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Er r or Rate vs. Signal-to-Noise Ratio
T he AD800 and AD802 were designed to operate with standard
ECL signal levels at the data input. Although not recom-
mended, smaller input signals are tolerable. Figure 8, 14, and
20 show the bit error rate performance versus input signal-to-
noise ratio for input signal amplitudes of full 900 mV ECL, and
decreased amplitudes of 80 mV and 20 mV. Wideband ampli-
tude noise is summed with the data signals as shown in Figure
2. T he full ECL and 80 mV signals give virtually indistinguish-
able results. T he 20 mV signals also provide adequate perfor-
mance when in lock, but signal acquisition may be impaired.
POWER
COMBINER
Jitter Tr ansfer
∑
DATA IN
T he PLL exhibits a low-pass filter response to jitter applied to
its input data.
0.47µF
0.47µF
50Ω
50Ω
DIFFERENTIAL
SIGNAL
SOURCE
D.U.T.
AD800/AD802
Bandwidth
T his describes the frequency at which the PLL attenuates
sinusoidal input jitter by 3 dB.
∑
DATA IN
POWER
COMBINER
75Ω
180Ω
1.0µF
P eaking
POWER
SPLITTER
T his describes the maximum jitter gain of the PLL in dB.
–5.2V
GND
D am ping Factor ,
describes how the PLL will track an input signal with a phase
step. A greater value of corresponds to less overshoot in the
ζ
100MHz – AD802-155
33MHz – AD800-52
FILTER
ζ
PLL response to a phase step.
order feedback systems.
ζ is a standard constant in second
NOISE
SOURCE
Acquisition Tim e
T his is the transient time, measured in bit periods, required for
the PLL to lock on input data from its free-running state.
Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:
Block Diagram
USING TH E AD 800 AND TH E AD 802 SERIES
Gr ound P lanes
Tr ansm ission Lines
Use of one ground plane for connections to both analog and
digital grounds is recommended. Output signal sensitivity to
power supply noise (PECL configuration, Figure 22) is less
using one ground plane than when using separate analog and
digital ground planes.
Use of 50 Ω transmission lines are recommended for DAT AIN,
CLKOUT , DAT AOUT , and FRAC signals.
Ter m inations
T ermination resistors should be used for DAT AIN, CLKOUT ,
DAT AOUT , and FRAC signals. Metal, thick film, 1% tolerance
resistors are recommended. T ermination resistors for the
DAT AIN signals should be placed as close as possible to the
DAT AIN pins.
P ower Supply Connections
Use of a 10 µF tantalum capacitor between VEE and ground is
recommended.
Use of 0.1 µF ceramic capacitors between IC power supply or
substrate pins and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to schematics, Figure 22 and Figure 26, for advised
connections.
Connections from VEE to lead resistors for DAT AIN, DAT A-
OUT , FRAC, and CLKOUT signals should be individual, not
daisy chained. T his will avoid crosstalk on these signals.
Loop D am ping Capacitor , C D
A ceramic capacitor may be used for the loop damping
capacitor.
Sensitivity of IC output signals (PECL configuration,
Figure 22) to high frequency power supply noise (at 2 ϫ the
nominal data rate) can be reduced through the connection of
signals AVCC and VCC1, and the addition of a bypass network.
T he type of bypass network to consider depends on the noise
tolerance required. T he more complex bypass network schemes
tolerate greater power supply noise levels. Refer to Figures 23
and 24 for bypassing schemes and power supply sensitivity
curves.
Input Buffer
Use of an input buffer, such as a 10H116 Line Receiver IC, is
suggested for an application where the DAT AIN signals do not
come directly from an ECL gate, or where noise immunity on
the DAT AIN signals is an issue.
–4–
REV. B
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