AD7816/AD7817/AD7818
AD7817 PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
CONVST
Logic Input Signal. The convert start signal. A 10-bit analog-to-digital conversion is initiated on the
falling edge of this signal. The falling edge of this signal places the track/hold in hold mode. The track/
hold goes into track mode again at the end of the conversion. The state of the CONVST signal is checked
at the end of a conversion. If it is logic low, the AD7817 will power-down—see Operating Mode section
of the data sheet.
2
3
BUSY
Logic Output. The busy signal is logic high during a temperature or voltage A/D conversion. The signal
can be used to interrupt a microcontroller when a conversion has finished.
Logic Output. The Overtemperature Indicator (OTI) is set logic low if the result of a conversion on
Channel 0 (Temperature Sensor) is greater that an 8-bit word in the Overtemperature Register (OTR).
The signal is reset at the end of a serial read operation, i.e., a rising RD/WR edge when CS is low.
OTI
4
CS
Logic Input Signal. The chip select signal is used to enable the serial port of the AD7817. This is neces-
sary if the AD7817 is sharing the serial bus with more than one device.
5
6
AGND
REFIN
Analog Ground. Ground reference for track/hold, comparator and capacitor DAC.
Analog Input. An external 2.5 V reference can be connected to the AD7817 at this pin. To enable the on-
chip reference the REFIN pin should be tied to AGND. If an external reference is connected to the
AD7817, the internal reference will shut down.
7–10
V
IN1 to VIN4
Analog Input Channels. The AD7817 has four analog input channels. The input channels are single-
ended with respect to AGND (analog ground). The input channels can convert voltage signals in the
range 0 V to VREF. A channel is selected by writing to the Address Register of the AD7817—see Control
Byte section.
11
12
13
VDD
DGND
DOUT
Positive Supply Voltage, 2.7 V to 5.5 V.
Digital Ground. Ground reference for digital circuitry.
Logic Output With a High Impedance State. Data is clocked out of the AD7817 serial port at this pin.
This output goes into a high impedance state on the falling edge of RD/WR or on the rising edge of the
CS signal, whichever occurs first.
14
15
DIN
SCLK
Logic Input. Data is clocked into the AD7817 at this pin.
Clock Input for the Serial Port. The serial clock is used to clock data into and out of the AD7817. Data is
clocked out on the falling edge and clocked in on the rising edge.
16
RD/WR
Logic Input Signal. The read/write signal is used to indicate to the AD7817 whether the data transfer
operation is a read or a write. The RD/WR should be set logic high for a read operation and logic low for
a write operation.
PIN CONFIGURATION
SOIC/TSSOP
1
2
CONVST
BUSY
O T I
16
15
RD/WR
SCLK
D
3
4
14
13
IN
AD7817
D
CS
OUT
TOP VIEW
(Not to Scale)
AGND
5
6
DGND
12
11
V
REF
IN
DD
V
V
7
8
10
9
IN4
IN1
V
V
IN3
IN2
–8–
REV. C