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AD7741BR PDF预览

AD7741BR

更新时间: 2024-02-16 00:10:56
品牌 Logo 应用领域
亚德诺 - ADI 转换器模拟特殊功能转换器光电二极管
页数 文件大小 规格书
12页 134K
描述
Single and Multichannel, Synchronous Voltage-to-Frequency Converters

AD7741BR 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
转换器类型:VOLTAGE TO FREQUENCY CONVERTERJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
最大线性误差 (EL):0.024%湿度敏感等级:1
功能数量:1端子数量:8
最大工作频率:6.144 MHz最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
最大正输入电压:2.5 V认证状态:Not Qualified
座面最大高度:2.59 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

AD7741BR 数据手册

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AD7741/AD7742  
The digital data that represents the analog input voltage is con-  
tained in the duty cycle of the pulse train appearing at the out-  
put of the comparator. The output is a fixed-width pulse whose  
frequency depends on the analog input signal. The input voltage  
is offset internally so that a full-scale input gives an output fre-  
quency of 0.45 fCLKIN and zero-scale input gives an output fre-  
quency of 0.05 fCLKIN. The output allows simple interfacing to  
either standard logic families or opto-couplers. The clock high  
period controls the pulsewidth of the frequency output. The  
pulse is initiated by the edge of the clock signal. The delay time  
between the edge of the clock and the edge of the frequency  
output is typically 9 ns. Figure 7 shows the waveform of this  
frequency output.  
AD7741/AD7742  
TO OTHER  
CIRCUITRY  
5M  
CLKIN  
C1  
CLKOUT  
C2  
Figure 8. On-Chip Oscillator  
The on-chip oscillator circuit also has a start-up time associated  
with it before it oscillates at its correct frequency and correct  
voltage levels. The typical start-up time for the circuit is 5 ms  
(with a 6.144 MHz crystal).  
After power-up, or if there is a step change in input voltage,  
there is a settling time that must elapse before valid data is  
obtained. This is typically 2 CLKIN cycles on the AD7742 and  
10 CLKIN cycles on the AD7741.  
The AD7741/AD7742 master clock appears on the CLKOUT  
pin of the device. The maximum recommended load on this pin  
is one CMOS load. When using a crystal to generate the AD7741/  
AD7742 clock it may be desirable to then use this clock as the  
clock source for the system. In this case it is recommended that  
the CLKOUT signal be buffered with a CMOS buffer before  
being applied to the rest of the circuit.  
f
CLKIN  
f
= f  
/4  
/2  
OUT  
V
CLKIN  
= V  
IN  
REF  
f
= f  
/10  
OUT  
CLKIN  
= V  
Reference Input  
V
/8  
IN  
REF  
The AD7741/AD7742 performs conversion relative to an applied  
reference voltage that allows easy interfacing to ratiometric  
systems. This reference may be applied using the internal 2.5 V  
bandgap reference. For the AD7741, this is done by simply  
leaving REFIN/OUT unconnected. For the AD7742, REFIN is  
tied to REFOUT. Alternatively, an external reference, e.g.,  
REF192 or AD780, may be used. For the AD7741, this is con-  
nected to REFIN/OUT and will overdrive the internal refer-  
ence. For the AD7742, it is connected directly to the REFIN  
pin.  
f
= f  
V
*3/20  
/4  
REF  
OUT  
CLKIN  
= V  
IN  
6 T  
7 T  
CLK  
CLK  
AVERAGE f  
VARIES BETWEEN f  
IS f  
*3/20 BUT THE ACTUAL PULSE STREAM  
OUT  
CLKIN  
/6 AND f  
/7  
CLKIN  
CLKIN  
Figure 7. AD7741/AD7742 Frequency Output Waveforms  
Clock Generation  
As distinct from the asynchronous VFCs which rely on the stability  
of an external capacitor to set their full-scale frequency, the  
AD7741/AD7742 uses an external clock to define the full-scale  
output frequency. The result is a more stable, more linear trans-  
fer function and also allows the designer to determine the sys-  
tem stability and drift based upon the external clock selected. A  
crystal oscillator may also be used if desired.  
While the internal reference will be adequate for most applica-  
tions, power supply rejection and overall regulation may be  
improved through the use of an external precision reference.  
The process of selecting an external voltage reference should  
include consideration of drive capability, initial error, noise and  
drift characteristics. A suitable choice would be the AD780 or  
REF192.  
The AD7741/AD7742 requires a master clock input, which may  
be an external CMOS-compatible clock signal applied to the  
CLKIN pin (CLKOUT not used). Alternatively, a crystal of the  
correct frequency can be connected between CLKIN and  
CLKOUT, when the clock circuit will function as a crystal  
controlled oscillator. Figure 8 shows a simple model of the on-  
chip oscillator.  
Power-Down Mode  
The low power standby mode is initiated by taking the PD pin  
low, which shuts down most of the analog and digital circuitry.  
This reduces the power consumption to 185 µW max.  
REV. 0  
–9–  

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