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AD7705BRZ-REEL7 PDF预览

AD7705BRZ-REEL7

更新时间： 2024-01-07 19:10:52
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器
页数 文件大小 规格书
44页 470K
描述
3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC

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AD7705BRZ-REEL7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknown风险等级：5.64
最大模拟输入电压：2.5 V最小模拟输入电压：-2.5 V
转换器类型：ADC, DELTA-SIGMAJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
最大线性误差 (EL)：0.003%湿度敏感等级：1
模拟输入通道数量：2位数：16
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：BINARY, OFFSET BINARY输出格式：SERIAL
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260采样速率：0.0192 MHz
座面最大高度：2.65 mm标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.5 mmBase Number Matches：1

AD7705BRZ-REEL7 数据手册

 浏览型号AD7705BRZ-REEL7的Datasheet PDF文件第5页浏览型号AD7705BRZ-REEL7的Datasheet PDF文件第6页浏览型号AD7705BRZ-REEL7的Datasheet PDF文件第7页浏览型号AD7705BRZ-REEL7的Datasheet PDF文件第9页浏览型号AD7705BRZ-REEL7的Datasheet PDF文件第10页浏览型号AD7705BRZ-REEL7的Datasheet PDF文件第11页 
AD7705/AD7706  
TIMING CHARACTERISTICS  
VDD = 2.7 V to 5.25 V; GND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.  
Table 2. Timing Characteristics1, 2  
Limit at TMIN, TMAX  
(B Version)  
Parameter  
Unit  
Conditions/Comments  
3, 4  
fCLKIN  
400  
2.5  
0.4 ꢀ tCLKIN  
0.4 ꢀ tCLKIN  
500 ꢀ tCLKIN  
100  
kHz min  
MHz max  
ns min  
ns min  
ns nom  
ns min  
Master clock frequency (crystal oscillator or externally supplied)  
For specified performance  
Master clock input low time, tCLKIN = 1/fCLKIN  
Master clock input high time  
DRDY high time  
tCLKIN LO  
tCLKIN HI  
t1  
t2  
RESET pulse width  
Read Operation  
t3  
t4  
0
ns min  
ns min  
ns min  
ns max  
ns max  
ns min  
ns min  
ns min  
ns min  
ns max  
ns max  
ns max  
DRDY to CS setup time  
120  
0
80  
100  
100  
100  
0
CS falling edge to SCLK rising edge setup time  
SCLK falling edge to data valid delay  
VDD = 5 V  
VDD = 3.0 V  
SCLK high pulse width  
5
t5  
t6  
t7  
t8  
SCLK low pulse width  
CS rising edge to SCLK rising edge hold time  
Bus relinquish time after SCLK rising edge  
VDD = 5 V  
VDD = 3.0 V  
SCLK falling edge to DRDY high7  
6
t9  
10  
60  
100  
100  
t10  
Write Operation  
t11  
t12  
t13  
t14  
t15  
t16  
120  
30  
20  
100  
100  
0
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
CS falling edge to SCLK rising edge setup time  
Data valid to SCLK rising edge setup time  
Data valid to SCLK rising edge hold time  
SCLK high pulse width  
SCLK low pulse width  
CS rising edge to SCLK rising edge hold time  
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
2 See Figure 19 and Figure 20.  
3 The fCLKIN duty cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7705/AD7706 are not in standby mode. If no clock is present, the devices can draw  
higher current than specified, and possibly become uncalibrated.  
4 The AD7705/AD7706 are production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). They are guaranteed by characterization to operate at 400 kHz.  
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.  
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then  
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus  
relinquish times of the part and as such are independent of external bus loading capacitances.  
7 DRDY  
DRDY  
returns high upon completion of the first read from the device after an output update. The same data can be reread while  
is high, but care should be  
taken that subsequent reads do not occur close to the next output update.  
I
(800μA AT V = 5V  
DD  
SINK  
100μA AT V = 3V)  
DD  
TO OUTPUT  
PIN  
1.6V  
50pF  
I
(200μA AT V = 5V  
DD  
100mA AT V = 3V)  
DD  
SOURCE  
Figure 2. Load Circuit for Access Time and Bus Relinquish Time  
Rev. C | Page 8 of 44  
 
 
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