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AD7705BRZ-REEL PDF预览

AD7705BRZ-REEL

更新时间： 2024-02-22 08:59:37
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 266K
描述
3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC

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AD7705BRZ-REEL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.02
最大模拟输入电压：2.5 V最小模拟输入电压：-2.5 V
转换器类型：ADC, DELTA-SIGMAJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
最大线性误差 (EL)：0.003%湿度敏感等级：1
模拟输入通道数量：2位数：16
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：BINARY, OFFSET BINARY输出格式：SERIAL
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
采样速率：0.0192 MHz座面最大高度：2.65 mm
子类别：Other Converters标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

AD7705BRZ-REEL 数据手册

 浏览型号AD7705BRZ-REEL的Datasheet PDF文件第3页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第4页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第5页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第7页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第8页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第9页 
AD7705/AD7706  
PIN CONFIGURATIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SCLK  
GND  
1
2
3
4
5
6
7
8
16 GND  
SCLK  
MCLK IN  
MCLK IN  
V
V
15  
14  
13  
12  
11  
10  
9
DD  
DD  
MCLK OUT  
DIN  
DIN  
MCLK OUT  
AD7705  
TOP VIEW  
(Not to Scale)  
AD7706  
TOP VIEW  
(Not to Scale)  
DOUT  
DOUT  
CS  
CS  
RESET  
DRDY  
DRDY  
RESET  
AIN2(+)  
AIN2(–)  
AIN3  
AIN1  
AIN1(+)  
AIN1(–)  
REF IN(–)  
REF IN(+)  
REF IN(–)  
REF IN(+)  
AIN2  
COMMON  
PIN FUNCTION DESCRIPTIONS  
Function  
Pin No.  
Mnemonic  
1
SCLK  
Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input  
to access serial data from the AD7705/AD7706. This serial clock can be a continuous clock  
with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon-  
tinuous clock with the information being transmitted to the AD7705/AD7706 in smaller  
batches of data.  
2
3
MCLK IN  
MCLK OUT  
Master Clock signal for the device. This can be provided in the form of a crystal/resonator or  
external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins.  
Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK  
OUT left unconnected. The part can be operated with clock frequencies in the range  
500 kHz to 5 MHz.  
When the master clock for the device is a crystal/resonator, the crystal/resonator is connected  
between MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK  
OUT provides an inverted clock signal. This clock can be used to provide a clock source for  
external circuitry and is capable of driving one CMOS load. If the user does not require it,  
this MCLK OUT can be turned off via the CLK DIS bit of the Clock Register. This ensures  
that the part is not burning unnecessary power driving capacitive loads on MCLK OUT.  
4
CS  
Chip Select. Active low Logic Input used to select the AD7705/AD7706. With this input  
hard-wired low, the AD7705/AD7706 can operate in its three-wire interface mode with  
SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device  
in systems with more than one device on the serial bus or as a frame synchronization signal in  
communicating with the AD7705/AD7706.  
5
6
7
8
9
RESET  
Logic Input. Active low input that resets the control logic, interface logic, calibration  
coefficients, digital filter and analog modulator of the part to power-on status.  
AD7705: Positive input of the differential Analog Input Channel 2. AD7706: Analog Input  
Channel 1.  
AD7705: Positive input of the differential Analog Input Channel 1. AD7706: Analog Input  
Channel 2.  
AD7705: Negative input of the differential Analog Input Channel 1. AD7706: COMMON  
Input. Analog inputs for Channels 1, 2 and 3 are referenced to this input.  
AIN2(+)[AIN1]  
AIN1(+)[AIN2]  
AIN1(–)[COMMON]  
REF IN(+)  
Reference Input. Positive input of the differential Reference Input to the AD7705/AD7706.  
The reference input is differential with the provision that REF IN(+) must be greater than  
REF IN(–). REF IN(+) can lie anywhere between VDD and GND.  
–6–  
REV. A  
1...3456789...32

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