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AD7705BRZ-REEL PDF预览

AD7705BRZ-REEL

更新时间： 2024-01-08 11:54:37
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 266K
描述
3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC

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AD7705BRZ-REEL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.02
最大模拟输入电压：2.5 V最小模拟输入电压：-2.5 V
转换器类型：ADC, DELTA-SIGMAJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
最大线性误差 (EL)：0.003%湿度敏感等级：1
模拟输入通道数量：2位数：16
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：BINARY, OFFSET BINARY输出格式：SERIAL
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
采样速率：0.0192 MHz座面最大高度：2.65 mm
子类别：Other Converters标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

AD7705BRZ-REEL 数据手册

 浏览型号AD7705BRZ-REEL的Datasheet PDF文件第1页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第2页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第3页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第5页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第6页浏览型号AD7705BRZ-REEL的Datasheet PDF文件第7页 
AD7705/AD7706  
(VDD = +2.7 V to +5.25 V; GND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = VDD  
unless otherwise noted.)  
TIMING CHARACTERISTICS1, 2  
Limit at TMIN, TMAX  
Parameter  
(B Version)  
Units  
Conditions/Comments  
3, 4  
fCLKIN  
400  
2.5  
0.4 × tCLKIN  
0.4 × tCLKIN  
500 × tCLKIN  
100  
kHz min  
MHz max  
ns min  
ns min  
ns nom  
ns min  
Master Clock Frequency: Crystal Oscillator or Externally Supplied  
for Specified Performance  
Master Clock Input Low Time. tCLKIN = 1/fCLKIN  
Master Clock Input High Time  
DRDY High Time  
RESET Pulsewidth  
tCLKIN LO  
tCLKIN HI  
t1  
t2  
Read Operation  
t3  
t4  
t5  
0
120  
0
ns min  
ns min  
ns min  
ns max  
ns max  
ns min  
ns min  
ns min  
ns min  
ns max  
ns max  
ns max  
DRDY to CS Setup Time  
CS Falling Edge to SCLK Rising Edge Setup Time  
SCLK Falling Edge to Data Valid Delay  
VDD = +5 V  
VDD = +3.0 V  
SCLK High Pulsewidth  
5
80  
100  
100  
100  
0
10  
60  
t6  
t7  
t8  
SCLK Low Pulsewidth  
CS Rising Edge to SCLK Rising Edge Hold Time  
Bus Relinquish Time after SCLK Rising Edge  
VDD = +5 V  
6
t9  
100  
100  
VDD = +3.0 V  
t10  
SCLK Falling Edge to DRDY High7  
Write Operation  
t11  
t12  
t13  
t14  
t15  
t16  
120  
30  
20  
100  
100  
0
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
CS Falling Edge to SCLK Rising Edge Setup Time  
Data Valid to SCLK Rising Edge Setup Time  
Data Valid to SCLK Rising Edge Hold Time  
SCLK High Pulsewidth  
SCLK Low Pulsewidth  
CS Rising Edge to SCLK Rising Edge Hold Time  
NOTES  
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
2See Figures 16 and 17.  
3fCLKIN Duty Cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7705/AD7706 is not in Standby mode. If no clock is present in this case, the device  
can draw higher current than specified and possibly become uncalibrated.  
4The AD7705/AD7706 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.  
5These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.  
6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is  
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the  
true bus relinquish times of the part and as such are independent of external bus loading capacitances.  
7DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care  
should be taken that subsequent reads do not occur close to the next output update.  
I
(800␮A AT V = +5V  
DD  
SINK  
100␮A AT V = +3V)  
DD  
TO OUTPUT  
PIN  
+1.6V  
50pF  
I
(200␮A AT V = +5V  
DD  
SOURCE  
100␮A AT V = +3V)  
DD  
Figure 1. Load Circuit for Access Time and Bus Relinquish Time  
–4–  
REV. A  
1234567...32

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