AD7357YRUZ

更新时间： 2024-01-12 00:43:54

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器光电二极管 PC
页数	文件大小	规格书
17页	196K
描述
Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

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技术参数
数据手册

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AD7357YRUZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.24
Samacsys Confidence：	3	Samacsys Status：	Released
2D Presentation：	https://componentsearchengine.com/2D/0T/578578.3.1.png	Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=578578
PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=578578	3D View：	https://componentsearchengine.com/viewer/3D.php?partID=578578
Samacsys PartID：	578578	Samacsys Image：	https://componentsearchengine.com/Images/9/AD7357YRUZ-RL.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/3/AD7357YRUZ-RL.jpg	Samacsys Pin Count：	16
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	16 PIN TSSOP	Samacsys Released Date：	2017-01-11 11:21:59
Is Samacsys：	N	最大模拟输入电压：	1.6 V
最小模拟输入电压：	0.5 V	最长转换时间：	0.238 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	5 mm
最大线性误差 (EL)：	0.0183%	湿度敏感等级：	1
模拟输入通道数量：	2	位数：	14
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出位码：	BINARY	输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	2.5 V	认证状态：	Not Qualified
采样速率：	4.2 MHz	采样并保持/跟踪并保持：	TRACK
座面最大高度：	1.2 mm	子类别：	Analog to Digital Converters
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
Base Number Matches：	1

AD7357YRUZ 数据手册

Preliminary Technical Data

AD7357

Once a data transfer is complete and SDATA_Aand SDATA_Bhave

returned to three-state, another conversion can be initiated after

MODES OF OPERATION

The mode of operation of the AD7357 is selected by controlling

the quiet time, t_QUIET, has elapsed by bringing

low again

the (logic) state of the

signal during a conversion. There are

(assuming the required acquisition time has been allowed).

three possible modes of operation: normal mode, partial power-

down mode and full power-down mode. After a conversion has

PARTIAL POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate and the ADC is then

powered down for a relatively long duration between these

bursts of several conversions. When the AD7357 is in partial

power-down, all analog circuitry is powered down except for

the on-chip reference and reference buffers.

been initiated, the point at which

which power-down mode, if any, the device enters. Similarly, if

is pulled high determines

already in a power-down mode,

can control whether the

device returns to normal operation or remains in power-down.

These modes of operation are designed to provide flexible

power management options. These options can be chosen to

optimize the power dissipation/throughput rate ratio for the

differing application requirements.

To enter partial power, the conversion process must be

NORMAL MODE

interrupted by bringing

high anywhere after the 2 falling

This mode is intended for applications needing fastest

throughput rates since the user does not have to worry about

any power-up times with the AD7357 remaining fully powered

at all times. Figure 14 shows the general diagram of the

operation of the AD7357 in this mode.

edge of SCLK and before the 10^thfalling edge of SCLK, as

shown in Figure 15. Once

window of SCLKs, the part enters partial power-down, the

has been brought high in this

conversion that was initiated by the falling edge of

terminated, and SDATA_Aand SDATA_Bgo back into three-state.

is brought high before the 2 SCLK falling edge, the part

remains in normal mode and does not power down. This avoids

accidental power-down due to glitches on the

line.

SCLK

OUT

LEADING ZEROS + CONVERSION RESULT

Figure 14. Normal Mode Operation

SCLK

The conversion is initiated on the falling edge of , as

THREE-STATE

OUT

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times,

must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

Figure 15. Entering Partial Power-Down Mode

CS CS

of . If

is brought high any time after the 10 SCLK falling

To exit this mode of operation and power up the AD7357 again,

a dummy conversion is performed. On the falling of , the

edge but before the 16^thSCLK falling edge, the part remains

powered up, but the conversion is terminated and SDATA_Aand

SDATA_Bgo back into three-state. 16 serial clock cycles are

required to complete the conversion and access the conversion

result for the AD7357. The SDATA lines do not return to three-

state after 16 SCLK cycles have elapsed, but instead do so when

device begins to power up, and continues to power up as long as

is held low until after the falling edge of the 10 SCLK. The

device is fully powered up after approximately TBD μs has

elapsed, and valid data results from the next conversion, as

shown in Figure 16. If

is brought high before the 2 falling

is brought high again. If

is left low for another 2 SCLK

edge of SCLK, the AD7357 again goes into partial power-down.

cycles, two trailing zeros are clocked out after the data. If

This avoids accidental power-up due to glitches on the

Although the device may begin to power up on the falling edge

CS CS

line.

left low for a further 16 SCLK cycles, the result for the other

ADC on board is also accessed on the same SDATA line as

shown in Figure 20 (see the Serial Interface section).

of , it powers down again on the rising edge of . If the

AD7357 is already in partial power-down mode and

brought high between the 2^ndand 10^thfalling edges of SCLK, the

device enters full power-down mode.

Once 32 SCLK cycles have elapsed, the SDATA line returns to

three-state on the 32 SCLK falling edge. If

is brought high

prior to this, the SDATA line returns to three-state at that point.

high again sometime prior to the next conversion if so desired,

since the bus still returns to three-state upon completion of the

dual result read.

FULL POWER-DOWN MODE

Thus,

may idle low after 32 SCLK cycles until it is brought

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, as power-up from a full power-down takes

substantially longer than that from a partial power-down. This

Rev. PrD | Page 13 of 17

1...10 11 121314 15 16 17

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