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AD7357BRUZ-RL

更新时间: 2024-02-14 05:34:39
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
17页 196K
描述
Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

AD7357BRUZ-RL 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.24
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/578578.3.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=578578
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=5785783D View:https://componentsearchengine.com/viewer/3D.php?partID=578578
Samacsys PartID:578578Samacsys Image:https://componentsearchengine.com/Images/9/AD7357YRUZ-RL.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/3/AD7357YRUZ-RL.jpgSamacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:16 PIN TSSOPSamacsys Released Date:2017-01-11 11:21:59
Is Samacsys:N最大模拟输入电压:1.6 V
最小模拟输入电压:0.5 V最长转换时间:0.238 µs
转换器类型:ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
最大线性误差 (EL):0.0183%湿度敏感等级:1
模拟输入通道数量:2位数:14
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出位码:BINARY输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5 V认证状态:Not Qualified
采样速率:4.2 MHz采样并保持/跟踪并保持:TRACK
座面最大高度:1.2 mm子类别:Analog to Digital Converters
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

AD7357BRUZ-RL 数据手册

 浏览型号AD7357BRUZ-RL的Datasheet PDF文件第4页浏览型号AD7357BRUZ-RL的Datasheet PDF文件第5页浏览型号AD7357BRUZ-RL的Datasheet PDF文件第6页浏览型号AD7357BRUZ-RL的Datasheet PDF文件第8页浏览型号AD7357BRUZ-RL的Datasheet PDF文件第9页浏览型号AD7357BRUZ-RL的Datasheet PDF文件第10页 
Preliminary Technical Data  
AD7357  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
INA+  
DRIVE  
V
SCLK  
SDATA  
SDATA  
DGND  
AGND  
CS  
INA-  
REF  
A
A
B
AD7357  
TOP VIEW  
(Not to Scale)  
REFGND  
AGND  
REF  
B
V
INB-  
V
V
INB+  
DD  
Figure 2. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No.  
Mnemonic Description  
VDD  
Power Supply Input. The VDD range for the AD7357 is 2.5V +/- 5ꢁ. The supply should be decoupled to AGND  
with a 0.1 µF capacitor and a 10 µF tantalum capacitor.  
16  
VDRIVE  
CS  
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will  
operate. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD  
.
10  
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the  
AD7357 and framing the serial data transfer.  
SCLK  
15  
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This  
clock is also used as the clock source for the conversion process.  
SDATAA,  
SDATAB  
14,13  
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on  
the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the  
AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of  
both ADCs. The data stream consists of one leading zero followed by the 14 bits of conversion data followed by  
a trailing zero. The data is provided MSB first. If CS is held low for 18 SCLK cycles rather than 16, then two  
further trailing zeros will appear after the 14 bits of data. If CS is held low for a further 18 SCLK cycles on either  
SDATAA or SDATAB , the data from the other ADC follows on the SDATA pin. This allows data from a  
simultaneous conversion on both ADCs to be gathered in serial format on either SDATAA or SDATAB.  
12  
DGND  
Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should  
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential  
and must not be more than 0.3 V apart, even on a transient basis.  
5, 11  
4
AGND  
Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input  
signals and should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the  
same potential and must not be more than 0.3 V apart, even on a transient basis.  
Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external  
reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between  
this pin and the REFA and REFB pins.  
Reference decoupling capacitor pins. Decoupling capacitors are connected between these pins and the  
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple the each  
reference pin with a 10µF capacitor. Provided the output is buffered, the on-chip reference can be taken from  
these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048V  
and this appears at these pins. These pins can also be overdriven by an external reference. The input voltage  
range for the external reference is 2.048+100mV to Vdd.  
REFGND  
REFA, REFB  
3, 6  
1, 2  
8, 7  
VINA-, VINA+  
VINB-, VINB+  
Analog Inputs of ADC A. These analog inputs form a fully differential pair.  
Analog Inputs of ADC B. These analog inputs form a fully differential pair.  
Rev. PrD | Page 7 of 17  

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