AD73322L
CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE
This section describes a typical sequence of control words that
would be sent to an AD73322L to configure it for operation in
mixed mode.1 It is not intended to be a definitive initialization
sequence, but shows users the typical input/output events that
occur in the programming and operation phases2. The text in
this section refers to the steps in Table 28.
subsequent interrupt service routine, the Tx register is loaded
with the control word for Channel 2. In Steps 9–10, Channels 1
and 2 are loaded with a control word setting for Control
Register B, which programs DMCLK = MCLK, the sampling
rate, to DMCLK/256, SCLK = DMCLK/2.
Steps 11 to 17 are similar to Steps 6 to 12 except that Control
Register C is programmed to power up all analog sections
(ADC, DAC, Reference = 1.2 V, REFOUT). In Steps 16–17,
DAC words are sent to the device—both DAC words are
necessary because each channel only updates its DAC when the
device has counted a number of SDIFS pulses, accompanied by
DAC words (in mixed mode, the MSB = 0), that are equal to the
device count field of Control Register A4. Because the channels
are in mixed mode, the serial port interrogates the MSB of the
16-bit word sent to determine whether it contains DAC data or
control information. DAC words should be sent in the sequence
Channel 2 followed by Channel 1.
Steps 1–5 detail the transfer of the control words to Control
Register A, which programs the device for mixed-mode
operation. Step 1 shows the first output sample event following
a device reset. The SDOFS signal is simultaneously raised on
both channels, which prepares the DSP Rx register to accept the
ADC word from Channel 2, while SDOFS from Channel 1
becomes an SDIFS to Channel 2. The cascade is configured as
nonFSLB, which means that the DSP has control over what is
transmitted to the cascade3 and, in this case, does not transmit
to the devices until both output words have been received from
the AD73322L.
Step 2 shows the status of the channels following receipt of the
Channel 2 output word. The DSP has received the ADC word
from Channel 2, while Channel 2 has received the output word
from Channel 1. At this stage, the SDOFS of Channel 2 is again
raised because Channel 2 has received Channel 1’s output word
and, as it is not addressed to Channel 2, passes it on to the DSP.
Steps 11 to17 show the control register update and DAC update
in a single sample period. Note that this combination is not
possible in the FSLB configuration3.
Steps 18 to 25 illustrate a control register readback cycle. In
Step 22, both channels have received a control word that
addresses Control Register C for readback (Bit 14 of the control
word = 1). When the channels receive the readback request, the
register contents are loaded to the serial registers, as shown in
Step 23. SDOFS is raised in both channels, which causes these
readback words to be shifted out toward the DSP. In Step 24,
the DSP has received the Channel 2 readback word, while
Channel 2 has received the Channel 1 readback word (note that
the address field in both words has been decremented to 111b).
In Step 25, the DSP has received the Channel 1 readback word
(its address field has been further decremented to 110b).
In Step 3, the DSP has received both ADC words. Typically, an
interrupt is generated following reception of the two output
words by the DSP (this involves programming the DSP to use
autobuffered transfers of two words). The transmit register of
the DSP is loaded with the control word destined for Channel 2.
This generates a transmit frame-sync (TFS) that is input to the
SDIFS input of the AD73322L to indicate the start of
transmission.
In Step 4, Channel 1 contains the control word destined for
Channel 2. The address field is decremented, SDOFS1 is raised
(internally) and the control word is passed on to Channel 2. The
Tx register of the DSP has now been updated with the control
word destined for Channel 1 (this can be done using auto-
buffering of transmit or by handling transmit interrupts
following each word sent).
Steps 26 to 30 detail an ADC and DAC update cycle using the
nonFSLB configuration. In this case, no control register update
is required.
1 Channel 1 and Channel 2 refer to the two AFE sections of the AD73322L.
2 This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. Ensure there is no latency (separation) between control words in a
cascade configuration. This is especially the case when programming
Control Registers A and B.
In Step 5, each channel has received a control word that
addresses Control Register A, sets the device count field equal
to two channels, and programs the channels into mixed mode
3 Mixed-mode operation with the FSLB configuration is more restricted in that
the number of words sent to the cascade equals the number of channels in
the cascade. This means that DAC updates may need to be substituted with
a register write or read. Using the FSLB configuration introduces a corruption
of the ADC samples in the sample period following a control register write.
This corruption is predictable and can be corrected in the DSP. The ADC
word is treated as a control word and the device address field is
decremented in each channel that it passes through before being returned
to the DSP.
(MM and
/DATA set to one).
PMG
Following Step 5, the device has been programmed into mixed
mode although none of the analog sections have been powered
up (controlled by Control Register C). Steps 6 to 10 detail
update of Control Register B in mixed mode. In Steps 6 to 8, the
ADC samples, which are invalid because the ADC section is not
yet powered up, are transferred to the DSP’s Rx section. In the
4 In mixed mode, DAC update is done using the same SDIFS counting scheme
as in normal data mode, with the exception that only DAC words (MSB set to
zero) are recognized as being able to increment the frame sync counters.
Rev. A | Page 43 of 48
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