AD73311LARS-REEL

更新时间： 2024-02-19 14:39:19

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亚德诺 - ADI		/
页数	文件大小	规格书
36页	333K
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AD73311LARS-REEL 数据手册

AD73311

Table II. Current Summary (AVDD = DVDD = +5.5 V)

Analog Internal Digital External Interface

MCLK

SE ON

Conditions

Current Current

Current

Total Current

Comments

ADC On Only

8.5

14.5

0.8

16.5

22.5

1.0

YES

REFOUT Disabled

ADC and DAC On

REFCAP On Only

REFCAP and

REFOUT On Only 3.5

1.5

3.5

1.7

YES

All Sections Off

MCLK Active Levels Equal to

0 V and DVDD

Digital Inputs Static and

Equal to 0 V or DVDD

0.01

0.02

The above values are in mA and are typical values unless otherwise noted.

Table III. Signal Ranges

3 V Power Supply

5VEN = 0

5 V Power Supply

5VEN = 1

5VEN = 0

1.2 V

V_REFCAP

V_REFOUT

ADC

1.2 V 10%

2.4 V

1.2 V

Maximum Input Range

at V_IN

1.578 V p-p

3.156 V p-p

Nominal Reference Level

1.0954 V p-p

2.1908 V p-p

DAC

Maximum Voltage

Output Swing

Single-Ended

1.578 V p-p

3.156 V p-p

1.578 V p-p

3.156 V p-p

6.312 V p-p

Differential

Nominal Voltage

Output Swing

Single-Ended

Differential

Output Bias Voltage

1.0954 V p-p

2.1909 V p-p

V_REFOUT

1.0954 V p-p

2.1909 V p-p

V_REFOUT

2.1908 V p-p

4.3818 V p-p

V_REFOUT

(AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; AGND = DGND = 0 V; T_A= T_MlNto T_MAX, unless

TIMING CHARACTERISTICS ^{otherwise noted)}

Limit at

T_A= –40؇C to +85؇C

Parameter

Unit

Description

Clock Signals

See Figure 1

MCLK Period

MCLK Width High

MCLK Width Low

t₁

t₂

t₃

24.4

ns min

Serial Port

t₄

t₅

t₆

t₇

t₈

t₉

t₁₀

t₁₁

t₁₂

t₁₃

See Figures 3 and 4

SCLK Period

SCLK Width High

SCLK Width Low

SDI/SDIFS Setup Before SCLK Low

SDI/SDIFS Hold After SCLK Low

SDOFS Delay from SCLK High

SDOFS Hold After SCLK High

SDO Hold After SCLK High

SDO Delay from SCLK High

SCLK Delay from MCLK

t₁

ns min

ns max

ns min

ns max

0.4 × t₁

REV. B

–6–

1...3 4 567 8 9...36

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