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AD7280WDSTZ

更新时间： 2024-02-22 22:50:53
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
38页 435K
描述
IC 6-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48, LEAD FREE, MS-026BBC, LQFP-48, Power Management Circuit

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AD7280WDSTZ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LEAD FREE, MS-026BBC, LQFP-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.82可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：S-PQFP-G48
长度：9 mm信道数量：6
功能数量：1端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH电源：7.5/30 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Power Management Circuits最大供电电流 (Isup)：10 mA
最大供电电压 (Vsup)：30 V最小供电电压 (Vsup)：7.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：9 mmBase Number Matches：1

AD7280WDSTZ 数据手册

 浏览型号AD7280WDSTZ的Datasheet PDF文件第6页浏览型号AD7280WDSTZ的Datasheet PDF文件第7页浏览型号AD7280WDSTZ的Datasheet PDF文件第8页浏览型号AD7280WDSTZ的Datasheet PDF文件第10页浏览型号AD7280WDSTZ的Datasheet PDF文件第11页浏览型号AD7280WDSTZ的Datasheet PDF文件第12页 
Preliminary Technical Data  
TERMINOLOGY  
AD7280  
Vin(n-1) frequency, fS, as  
CMRR (dB) = 10 log (Pf/PfS)  
Differential Nonlinearity  
This is the difference between the measured and the ideal 1 LSB  
change between any two adjacent codes in the ADC.  
where Pf is the power at frequency f in the ADC output, and PfS  
is the power at frequency fS in the ADC output.  
Integral Nonlinearity  
Power Supply Rejection Ration (PSRR)  
This is the maximum deviation from a straight line passing  
through the endpoints of the ADC transfer function. The  
endpoints of the transfer function are zero scale (a point 1 LSB  
below the first code transition) and full scale (a point 1 LSB above  
the last code transition).  
Variations in power supply affect the full-scale transition but  
not the converter’s linearity. PSRR is the maximum change in  
the full-scale transition point due to a change in power supply  
voltage from the nominal value.  
Reference Voltage Temperature Coefficient  
Offset Code Error  
Reference voltage temperature coefficient is derived from the  
maximum and minimum reference output voltage (VREF  
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C  
using the following equation:  
This applies to straight binary output coding. It is the deviation  
of the first code transition (00 ... 000) to (00 ... 001) from the  
ideal, that is, AGND +1 LSB for VT1 to VT6 and 1V + AGND  
+1 LSB for Vin0 to Vin6.  
)
VREF ( Max)–VREF (Min)  
REF (25°C) × (TMAX –TMIN )  
×106  
Gain Error  
TCVREF (ppm/°C) =  
V
This applies to straight binary output coding. It is the deviation  
of the last code transition (111 ... 110) to (111 ... 111) from the  
ideal (that is 2 × VREF − 1 LSB) after adjusting for the offset  
error.  
where:  
V
V
V
T
T
REF(Max) = Maximum VREF at TMIN, T(25°C), or TMAX  
REF(Min) = Minimum VREF at TMIN, T(25°C), or TMAX  
REF(25°C) = VREF at +25°C  
ADC Unadjusted Error  
ADC Unadjusted Error includes integral nonlinearity errors,  
offset and gain errors of the ADC and measurement channel.  
MAX = +85°C  
MIN = –40°C  
Output Voltage Hysteresis  
Total Unadjusted Error (TUE)  
This is the maximum deviation of the output code from the  
ideal. Total Unadjusted Error includes integral nonlinearity  
errors, offset and gain errors and reference drift.  
Output voltage hysteresis, or thermal hysteresis, is defined as  
the absolute maximum change of reference output voltage after  
the device is cycled through temperature from either  
Offset Error Match  
This is the difference in zero code error across all 6 channels.  
T_HYS+ = +25°C to TMAX to +25°C  
T_HYS– = +25°C to TMIN to +25°C  
Gain Error Match  
The difference in gain error across all 6 channels.  
It is expressed in ppm using the following equation:  
V
REF (25°C) −VREF (T _ HYS)  
V
HYS (ppm) =  
× 106  
Track-and-Hold Acquisition Time  
V
REF (25°C)  
The track-and-hold amplifier returns to track mode at the end  
of a conversion. Track-and-hold acquisition time is the time  
required for the output of the track-and-hold amplifier to reach  
its final value, within ±± LSB.  
where:  
REF(25°C) = VREF at 25°C  
VREF(T_HYS) = Maximum change of VREF at T_HYS+ or  
V
T_HYS–.  
Common Mode Rejection Ration (CMRR)  
CMRR is defined as the ratio of the power in the ADC output  
at full-scale frequency, f, to the power of a 100 mV sine wave  
applied to the common-mode voltage of the Vin(n) and  
Rev. PrF| Page 9 of 38  
1...6789101112...38

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