AD7265
SERIAL INTERFACE
Figure 41 shows the detailed timing diagram for serial inter-
facing to the AD7265. The serial clock provides the conversion
clock and controls the transfer of information from the AD7265
during conversion.
A minimum of 14 serial clock cycles are required to perform
the conversion process and to access data from one conversion
CS
on either data line of the AD7265.
going low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Therefore, the first
falling clock edge on the serial clock has the leading zero pro-
vided and also clocks out the second leading zero. The 12-bit
result then follows with the final bit in the data transfer valid on
the 14th falling edge, having being clocked out on the previous
(13th) falling edge. It may also be possible to read in data on
each SCLK rising edge depending on the SCLK frequency or
CS
The
signal initiates the data transfer and conversion process.
CS
The falling edge of
puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once 13
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in Figure 41
at Point B. If a 16-SCLK transfer is used, then two trailing zeros
CS
the supply voltage. The first rising edge of SCLK after the
CS
will appear after the final LSB. On the rising edge of , the
conversion is terminated and DOUTA and DOUTB go back into
falling edge would have the second leading zero provided, and
the 13th rising SCLK edge would have DB0 provided.
CS
three-state. If
is not brought high but is instead held low for
Note that with fast SCLK values, and thus short SCLK periods,
in order to allow adequately for t2, an SCLK rising edge may
occur before the first SCLK falling edge. This rising edge of
SCLK can be ignored for the purposes of the timing descriptions in
this section. If a falling edge of SCLK is coincident with the
a further 14 (or 16) SCLK cycles on DOUTA, the data from Con-
version B is output on DOUTA (followed by 2 trailing zeros).
CS
Likewise, if
is held low for a further 14 (or 16) SCLK cycles
on DOUTB, the data from Conversion A is output on DOUTB. This
is illustrated in Figure 42 where the case for DOUTA is shown. In
CS
falling edge of , then this falling edge of SCLK is not
this case, the DOUT line in use goes back into three-state on the
acknowledged by the AD7265, and the next falling edge of
nd
CS
32 SCLK falling edge or the rising edge of , whichever
CS
SCLK will be the first registered after the falling edge of
.
occurs first.
CS
t9
t2
t6
B
SCLK
3
4
5
1
2
13
t5
tQUIET
t8
t7
t3
t4
D
D
A
B
OUT
OUT
0
DB11
DB10
DB2
0
DB9
DB8
DB1
DB0
THREE-STATE
THREE-
STATE
2 LEADING ZEROS
Figure 41. Serial Interface Timing Diagram
CS
t6
t2
SCLK
3
4
5
1
2
14
15
16
17
32
t5
t10
t3
t4
t7
DB11
DB10
DB9
DB11
B
0
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
D
A
A
A
A
OUT
THREE-
STATE
THREE-
STATE
2 TRAILING ZEROS
2 LEADING ZEROS
2 LEADING
ZEROS
2 TRAILING ZEROS
Figure 42. Reading Data from Both ADCs on One DOUT Line with 32 SCLKs
Rev. A | Page 22 of 28
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