1 MSPS, 14-Bit, Simultaneous Sampling
SAR ADC with PGA and Four Comparators
Data Sheet
AD7264
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AV
V
A
CC
REF
Dual, simultaneous sampling, 14-bit, 2-channel ADC
True differential analog inputs
Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,
×24, ×32, ×48, ×64, ×96, ×128
Throughput rate per ADC
REF
AD7264
BUF
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
V
+
–
A
OUTPUT
DRIVERS
D
A
PGA
T/H
OUT
A
1 MSPS for AD7264
500 kSPS for AD7264-5
SCLK
CAL
CS
Analog input impedance: >1 GΩ
Wide input bandwidth
−3 dB bandwidth: 1.7 MHz at gain = 2
4 on-chip comparators
REFSEL
CONTROL
LOGIC
G0
G1
G2
G3
V
DRIVE
SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32
Device offset calibration
System gain calibration
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
V
+
–
B
OUTPUT
DRIVERS
D
B
T/H
PGA
OUT
B
PD0/D
PD1
PD2
IN
On-chip reference: 2.5 V
BUF
−40°C to +105°C operation
V
B
REF
High speed serial interface
C
_C V
B CC
A
C
+
A
Compatible with SPI, QSPI™, MICROWIRE™, and DSP
48-lead LFCSP and LQFP packages
OUTPUT
C
C
A
OUT
DRIVERS
C
C
C
–
+
–
A
B
B
COMP
OUTPUT
DRIVERS
B
OUT
COMP
C
_C _GND
A
B
GENERAL DESCRIPTION
C
_C V
D CC
C
C
C
C
C
+
–
+
–
C
C
D
D
OUTPUT
DRIVERS
C
C
C
D
The AD7264 is a dual, 14-bit, high speed, low power, successive
approximation ADC that operates from a single 5 V power supply
and features throughput rates of up to 1 MSPS per on-chip ADC
(500 kSPS for the AD7264-5). Two complete ADC functions
allow simultaneous sampling and conversion of two channels.
Each ADC is preceded by a true differential analog input with a
PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6,
×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.
OUT
COMP
OUTPUT
DRIVERS
OUT
COMP
C
_C _GND
C
D
AGND
DGND
Figure 1.
PRODUCT HIGHLIGHTS
The AD7264 contains four comparators. Comparator A and
Comparator B are optimized for low power, whereas Comparator C
and Comparator D have fast propagation delays. The AD7264
features a calibration function to remove any device offset error
and programmable gain adjust registers to allow for input path
(for example, sensor) offset and gain compensation. The AD7264
has an on-chip 2.5 V reference that can be disabled if an external
reference is preferred. The AD7264 is available in 48-lead LFCSP
and LQFP packages.
1. Integrated PGA with a variety of flexible gain settings to
allow detection and conversion of low level analog signals.
2. Each PGA is followed by a dual simultaneous sampling
ADC, featuring throughput rates of 1 MSPS per ADC
(500 kSPS for the AD7264-5). The conversion result of
both ADCs is simultaneously available on separate data
lines or in succession on one data line if only one serial
port is available.
3. Four integrated comparators that can be used to count
signals from pole sensors in motor control applications.
4. Internal 2.5 V reference.
The AD7264 is ideally suited for monitoring small amplitude
signals from a variety of sensors. The parts include all the
functionality needed for monitoring the position feedback signals
from a variety of analog encoders used in motor control systems.
Rev. B
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