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AD7150BRMZ-REEL

更新时间： 2024-01-28 19:25:10

品牌	Logo	应用领域
亚德诺 - ADI		转换器消费电路商用集成电路光电二极管
页数	文件大小	规格书
28页	986K
描述
Ultra-Low Power, 2-Channel, Capacitance Converter for Proximity Sensing

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AD7150BRMZ-REEL 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	10
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	0.77
Is Samacsys：	N	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PDSO-G10	JESD-609代码：	e3
长度：	3 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	10
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.1 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3 mm	Base Number Matches：	1

AD7150BRMZ-REEL 数据手册

AD7150

Parameter

Min

Typ

Max

Unit¹

Test Conditions/Comments

POWER REQUIREMENTS

V_DD-to-GND Voltage

I_DDCurrent⁴

2.7

3.6

120

V_DD= 3.3 V, nominal

100

μA

I_DDCurrent Power-Down Mode⁴

Temperature ≤ 25°C

Temperature = 85°C

¹Capacitance units: one picofarad (1 pF) = 1 × 10⁻¹²farad (F); one femtofarad (1 fF) = 10⁻¹⁵farad (F).

²The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can therefore be up to the sum of the CAPDAC value and the conversion

input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC

nominal input range.

³Specification is not production tested but is supported by characterization data at initial product release.

⁴Digital inputs equal to V_DDor GND.

TIMING SPECIFICATIONS

V_DD= 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = V_DD; –40°C to +85°C, unless otherwise noted.

Table 2.

Parameter

Min Typ Max

Unit

Test Conditions/Comments

CONVERTER

Conversion Time

Both channels, 5 ms per channel.

Wake-Up Time from Power-Down Mode^{1, 2}

Power-Up Time^{1, 3}

0.15

Reset Time^{1, 4}

SERIAL INTERFACE^{5, 6}

See Figure 2.

SCL Frequency

0.6

1.3

400

kHz

μs

SCL High Pulse Width, t_HIGH

SCL Low Pulse Width, t_LOW

SCL, SDA Rise Time, t_R

0.3

SCL, SDA Fall Time, t_F

Hold Time (Start Condition), t_HD;STA

Setup Time (Start Condition), t_SU;STA

Data Setup Time, t_SU;DAT

Setup Time (Stop Condition), t_SU;STO

Data Hold Time (Master), t_HD;DAT

Bus-Free Time (Between Stop and Start Condition), t_BUF

0.6

0.1

0.6

After this period, the first clock is generated.

Relevant for repeated start condition.

1.3

¹Specification is not production tested but is supported by characterization data at initial product release.

²Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.

³Power-up time is the maximum delay between the V_DDcrossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface

command.

⁴Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface

command.

⁵Sample tested during initial release to ensure compliance.

⁶All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Output load = 10 pF.

t_R

t_F

t_LOW

t_HD;STA

SCL

SDA

t_HIGH

t_SU;STA

t_SU;STO

t_HD;STA

t_HD;DAT

t_SU;DAT

t_BUF

Figure 2. Serial Interface Timing Diagram

Rev. 0 | Page 4 of 28

1 2 345 6 7...28

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