AD7011
BIN
TxCLK
X
Y
1
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
X
Y
TxDATA
BOUT
1
N
N
N+1
N+1
N+2
N+2
N+3
N+3
N+4
N+4
N+5
N+5
N+6
N+6
N+7
N+7
N+8 N+8
= 480t1
(ITx–ITx),
(QTx–QTx)
3 SYMBOL
RAMP-UP ENVELOPE
3 SYMBOL
RAMP-DOWN ENVELOPE
I
I
I
I
I
I
N+4
0
0
0
0
SYMBOL
1
N
N+1
N+2
N+3
0
Q
Q
Q
Q
Q
Q
N+4
0
1
N
N+1
N+2
N+3
PHASE MAX
EFFECT
Figure 12. Transm it Burst
As Figure 12 illustrates, the ramp-down envelope reaches zero
after three symbols, hence the fourth symbol does not actually
get transmitted.
When POWER is brought low this puts the transmit section into
a low power sleep mode, drawing minimal current. T he analog
outputs go high impedance while in low power sleep mode.
Reconstr uction Filter s
MODE1 = VDD; MODE2 = DGND: Analog Mode
T he reconstruction filters smooth the DAC output signals,
providing continuous time I and Q waveforms at the output
pins. T hese are 4th order Bessel low-pass filters with a –3 dB
frequency of approximately 25 kHz. T he filters are designed to
have a linear phase response in the passband and due to the
reconstruction filters being on-chip, the phase mismatch
between the I and Q transmit channels is kept to a minimum.
Figure 6 shows the timing diagram for the transmit interface
when operating in analog mode. In this mode the π/4 DQPSK
modulator is bypassed and direct access to the I and Q 10-bit
DACs is provided. Loading of the I and Q DACs is accom-
plished using a 4 wire 16-bit serial interface. T he pins T xCLK,
T xDAT A and BIN are all reconfigured as inputs, with the
functions of FRAME, IDAT A and QDAT A respectively.
Tr ansm it Section D igital Inter face
I and Q data are loaded via the IDAT A and QDAT A pins and
FRAME synchronizes the loading of the 16-bit I and Q words.
FRAME should be brought high one clock cycle prior to the I
and Q MSBs. Data is latched on the rising edge of MCLK,
MSB first, where only the first 10 data bits are significant. Con-
tinuous updating of the I and Q DACs is required at a rate of
MCLK/16.
MODE1 = MODE2 = DGND: Digital π/4 DQPSK Mode
Figures 4 and 5 shows the timing diagrams for the transmit
interface when operating in T IA π/4 DQPSK mode. POWER is
sampled on the rising edge of MCLK. When POWER is
brought high, the transmit section is brought out of sleep mode
and initiates a self-calibration routine as described above. Once
the self-calibration is complete, the READY signal goes high to
indicate that a transmit burst can now begin. BIN (Burst in) is
brought high to initiate a transmit burst and should only be
brought high if the READY signal is already high.
MODE1 = DGND; MODE2 = VDD: Frequency Test Mode
A special FT EST (Frequency T EST ) mode is provided for the
customer, where no phase modulation takes place and the mod-
ulator outputs remain static. ITx is set to zero and QTx is set to
full scale as Figure 7 illustrates. However, the normal ramp-up/
down envelope is still applied during the beginning and end of a
burst.
When BIN goes high, the READY signal goes low on the next
rising edge of MCLK and T xCLK becomes active after a
further three MCLK cycles. T xCLK can be used to clock out
the transmit data from the ASIC or DSP on the rising edge of
T xCLK and the AD7011 will latch T xDAT A on the falling
edge of T xCLK.
MODE1 = MODE2 = VDD: Factory Test Mode
T his mode is reserved for factory test only and should not be
used by the customer for correct device operation.
When BIN is brought low, the AD7011 will continue to clock in
the current Di-bit symbol (XN + 4, YN + 4) and will continue for a
further 8 T xCLK cycles (four symbols). After the final T xCLK,
READY goes high waiting for BIN to be brought high to begin
the next transmit burst.
–10–
REV. B
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