AD670KNZ

更新时间： 2024-02-20 07:12:53

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	366K
描述
IC 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP20, PLASTIC, DIP-20, Analog to Digital Converter

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AD670KNZ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.91	最大模拟输入电压：	2.55 V
转换器类型：	A/D CONVERTER	JESD-30 代码：	S-XQCC-N20
JESD-609代码：	e0	最大线性误差 (EL)：	0.4%
位数：	8	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出位码：	OFFSET BINARY
封装主体材料：	CERAMIC	封装代码：	QCCN
封装等效代码：	LCC20,.35SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	5 V
认证状态：	Not Qualified	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
Base Number Matches：	1

AD670KNZ 数据手册

AD670

STAND-ALONE OPERATION

The AD670 can be used in a “stand-alone” mode, which is use-

ful in systems with dedicated input ports available. Two typical

conditions are described and illustrated by the timing diagrams

which follow.

Single Conversion, Single Read

When the AD670 is used in a stand-alone mode, CS and CE

should be tied together. Conversion will be initiated by bringing

R/W low. Within 700 ns, a conversion will begin. The R/W

pulse should be brought high again once the conversion has

started so that the data will be valid upon completion of the

conversion. Data will remain valid until CE and CS are brought

high to indicate the end of the read cycle or R/W goes low. The

timing diagram is shown in Figure 10.

Figure 8. Write/Convert Start Timing

The R/W line is used to direct the converter to start a conver-

sion (R/W low) or read data (R/W high). The relative sequenc-

ing of the three control signals (R/W, CE, CS) is unimportant.

However, when all three signals remain low for at least 300 ns

(t_W), STATUS will go high to signal that a conversion is taking

place.

Once a conversion is started and the STATUS line goes high,

convert start commands will be ignored until the conversion

cycle is complete. The output data buffer cannot be enabled

during a conversion.

Read Cycle

Figure 9 shows the timing for the data read operation. The data

outputs are in a high impedance state until a read cycle is initi-

ated. To begin the read cycle, R/W is brought high. During a

read cycle, the minimum pulse length for CE and CS is a func-

tion of the length of time required for the output data to be

valid. The data becomes valid and is available to the data bus in

a maximum of 250 ns. This delay between the high impedance

Figure 10. Stand-Alone Mode Single Conversion/

Single Read

Continuous Conversion, Single Read

A variety of applications may call for the A/D to be read after

several conversions. In process control systems, this is often the

case since a reading from a sensor may only need to be updated

every few conversions. Figure 11 shows the timing relationships.

state and valid data is the maximum bus access time or t_TD

Bringing CE or CS high during valid data ends the read cycle.

The outputs remain valid for a minimum of 25 ns (t_DH) and re-

turn to the high impedance state after a delay, t_DT, of 150 ns

maximum.

Once again, CE and CS should be tied together. Conversion

will begin when the R/W signal is brought low. The device will

convert repeatedly as indicated by the status line. A final con-

version will take place once the R/W line has been brought high.

The rising edge of R/W must occur while STATUS is high. R/W

should not return high while STATUS is low since the circuit is

in a reset state prior to the next conversion. Since the rising

edge of R/W must occur while STATUS is high, R/W’s length

must be a minimum of 10.25 µs (t_C+ t_TD). Data becomes valid

upon completion of the conversion and will remain so until the

CE and CS lines are brought high indicating the end of the read

cycle or R/W goes low initiating a new series of conversions.

Figure 9. Read Cycle Timing

Figure 11. Stand-Alone Mode Continuous Conversion/

Single Read

REV. A

–8–

1...5 6 789 10 11 12

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