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AD6684BCPZ-500

更新时间： 2024-02-15 22:42:13
品牌 Logo 应用领域
亚德诺 - ADI 电信电信集成电路
页数 文件大小 规格书
108页 3043K
描述
135 MHz Quad IF Receiver

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中文翻译

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AD6684BCPZ-500 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：72Reach Compliance Code：compliant
风险等级：2.2JESD-30 代码：S-XQCC-N72
JESD-609代码：e3长度：10 mm
湿度敏感等级：3功能数量：1
端子数量：72封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
座面最大高度：1 mm标称供电电压：0.975 V
表面贴装：YES电信集成电路类型：TELECOM CIRCUIT
端子面层：Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：10 mm
Base Number Matches：1

AD6684BCPZ-500 数据手册

 浏览型号AD6684BCPZ-500的Datasheet PDF文件第2页浏览型号AD6684BCPZ-500的Datasheet PDF文件第3页浏览型号AD6684BCPZ-500的Datasheet PDF文件第4页浏览型号AD6684BCPZ-500的Datasheet PDF文件第5页浏览型号AD6684BCPZ-500的Datasheet PDF文件第6页浏览型号AD6684BCPZ-500的Datasheet PDF文件第7页 
135 MHz Quad IF Receiver  
AD6684  
4 integrated wideband digital downconverters (DDCs)  
48-bit numerically controlled oscillator (NCO), up to  
4 cascaded half-band filters  
1.4 GHz analog input full power bandwidth  
Amplitude detect bits for efficient automatic gain control  
(AGC) implementation  
Differential clock input  
Integer clock divide by 1, 2, 4, or 8  
Data Sheet  
FEATURES  
JESD204B (Subclass 1) coded serial digital outputs  
Lane rates up to 15 Gbps  
1.68 W total power at 500 MSPS  
420 mW per analog-to-digital converter (ADC) channel  
SFDR = 82 dBFS at 305 MHz (1.8 V p-p input range)  
SNR = 66.8 dBFS at 305 MHz (1.8 V p-p input range)  
Noise density = −151.5 dBFS/Hz (1.8 V p-p input range)  
Analog input buffer  
On-chip dithering to improve small signal linearity  
Flexible differential input range  
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)  
82 dB channel isolation/crosstalk  
0.975 V, 1.8 V, and 2.5 V dc supply operation  
Noise shaping requantizer (NSR) option for main receiver  
Variable dynamic range (VDR) option for digital  
predistortion (DPD)  
On-chip temperature diode  
Flexible JESD204B lane configurations  
APPLICATIONS  
Communications  
Diversity multiband, multimode digital receivers  
3G/4G, W-CDMA, GSM, LTE, LTE-A  
HFC digital reverse path receivers  
Digital predistortion observation paths  
General-purpose software radios  
FUNCTIONAL BLOCK DIAGRAM  
AVDD2  
(1.8V)  
AVDD3  
(2.5V)  
AVDD1 AVDD1_SR  
DVDD  
DRVDD1 DRVDD2  
SPIVDD  
(1.8V)  
(0.975V)  
(0.975V)  
(0.975V) (0.975V)  
(1.8V)  
SIGNAL PROCESSING  
BUFFER  
14  
VIN+A  
ADC  
CORE  
DIGITAL DOWNCONVERTER  
(×2)  
VIN–A  
VCM_AB  
FD_A  
2
JESD204B  
HIGH SPEED  
SERIALIZER  
SERDOUTAB0±  
SERDOUTAB1±  
Tx  
OUTPUTS  
NOISE SHAPED REQUANTIZER  
(×2)  
FAST  
DETECT  
SIGNAL  
MONITOR  
FD_B  
BUFFER  
VARIABLE DYNAMIC RANGE  
(×2)  
14  
VIN+B  
VIN–B  
ADC  
CORE  
SIGNAL MONITOR  
AND FAST DETECT  
SYSREF±  
JESD204B  
SUBCLASS 1  
CONTROL  
CLOCK  
GENERATION  
SYNCINB±AB  
SYNCINB±CD  
CLK+  
CLK–  
÷2  
÷4  
÷8  
SIGNAL PROCESSING  
BUFFER  
14  
VIN+C  
ADC  
CORE  
DIGITAL DOWNCONVERTER  
(×2)  
VIN–C  
VCM_CD  
FD_C  
2
JESD204B  
HIGH SPEED  
SERIALIZER  
SERDOUTCD0±  
SERDOUTCD1±  
Tx  
NOISE SHAPED REQUANTIZER  
(×2)  
OUTPUTS  
FAST  
DETECT  
SIGNAL  
MONITOR  
FD_D  
VARIABLE DYNAMIC RANGE  
(×2)  
BUFFER  
14  
VIN+D  
VIN–D  
ADC  
CORE  
SPI CONTROL  
PDWN/STBY  
AD6684  
AGND DRGND  
SDIO  
SCLK CSB  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2016 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
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中文翻译

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AD6684BCPZ-500 替代型号

型号 品牌 替代类型 描述 数据表
AD6684BCPZRL7-500 ADI

完全替代

 135 MHz Quad IF Receiver

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