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AD6688BBPZRL-3000 PDF预览

AD6688BBPZRL-3000

更新时间： 2024-02-13 21:44:51
品牌 Logo 应用领域
亚德诺 - ADI 电信电信集成电路
页数 文件大小 规格书
138页 2535K
描述
RF Diversity and 1.2 GHz Bandwidth Observation Receiver

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AD6688BBPZRL-3000 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：LFBGA,
针数：196Reach Compliance Code：compliant
风险等级：5.69JESD-30 代码：S-PBGA-B196
长度：12 mm湿度敏感等级：3
功能数量：1端子数量：196
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260座面最大高度：1.53 mm
标称供电电压：0.975 V表面贴装：YES
电信集成电路类型：RF AND BASEBAND CIRCUIT温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：12 mmBase Number Matches：1

AD6688BBPZRL-3000 数据手册

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RF Diversity and 1.2 GHz Bandwidth  
Observation Receiver  
AD6688  
Data Sheet  
Two Integrated wideband digital processors per channel  
FEATURES  
48-bit NCO  
JESD204B (Subclass 1) coded serial digital outputs  
Support for lane rates up to 16 Gbps per lane  
1.7 W total power per channel at 3 GSPS (default settings)  
Performance at −2 dBFS amplitude, 2.6 GHz input  
SFDR = 70 dBFS  
NSD = −148.0 dBFS/Hz  
Performance at −9 dBFS amplitude, 2.6 GHz input  
SFDR = 75 dBFS  
4 cascaded half band filters  
Phase coherent NCO switching  
Up to 4 channels available  
Serial port control  
Integer clock divide by 2 and divide by 4  
Flexible JESD204B lane configurations  
On-chip dither  
NSD = −151.4 dBFS/Hz  
Integrated input buffer  
APPLICATIONS  
Diversity multiband, multimode digital receivers  
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A  
DOCSIS 3.0 CMTS upstream receive paths  
HFC digital reverse path receivers  
Noise density = −152.0 dBFS/Hz  
0.975 V, 1.9 V, and 2.5 V dc supply operation  
9 GHz analog input full power bandwidth (−3 dB)  
Amplitude detect bits for efficient AGC implementation  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1  
(0.975V)  
AVDD2  
(1.9V)  
AVDD3  
(2.5V)  
AVDD1_SR  
(0.975V)  
DVDD  
DRVDD1  
(0.975V)  
DRVDD2  
(1.9V)  
SPIVDD  
(1.9V)  
(0.975V)  
BUFFER  
SIGNAL PROCESSING  
VIN+A  
VIN–A  
ADC  
DIGITAL DOWN CONVERSION  
SERDOUT0±  
SERDOUT1±  
SERDOUT2±  
SERDOUT3±  
SERDOUT4±  
SERDOUT5±  
SERDOUT6±  
SERDOUT7±  
DIGITAL DOWN CONVERSION  
DIGITAL DOWN CONVERSION  
DIGITAL DOWN CONVERSION  
JESD204B  
FAST  
SIGNAL  
MONITOR  
DATA  
ROUTER  
MUX  
DATA  
ROUTER  
MUX  
LINK  
AND  
8
DETECT  
TX  
OUTPUTS  
PDWN/  
STBY  
BUFFER  
VIN+B  
VIN–B  
VREF  
ADC  
GPIO_A0/GPIO_A1 GPIO_B0/GPIO_B1  
NCO BAND SELECT  
SYNCINB±  
FD_A/GPIO_A0  
GPIO_A1  
CLOCK  
DISTRIBUTION  
CLK+  
CLK–  
JESD204B  
SUBCLASS1  
CONTROL  
GPIO MUX  
FD_B/GPIO_B0  
GPIO_B1  
AD6688  
SPI CONTROL  
÷2  
÷4  
AGND  
SYSREF±  
SDIO SCLK CSB  
DGND  
DRGND  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2017 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
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