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AD6679BBPZ-500 PDF预览

AD6679BBPZ-500

更新时间: 2024-01-07 07:08:03
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亚德诺 - ADI /
页数 文件大小 规格书
82页 1723K
描述
135 MHz BW IF Diversity Receiver

AD6679BBPZ-500 数据手册

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135 MHz BW IF Diversity Receiver  
Data Sheet  
AD6679  
FEATURES  
APPLICATIONS  
Parallel LVDS (DDR) outputs  
Diversity multiband, multimode digital receivers  
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A  
DOCSIS 3.0 CMTS upstream receive paths  
HFC digital reverse path receivers  
In-band SFDR = 82 dBFS at 340 MHz (500 MSPS)  
In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS)  
1.1 W total power per channel at 500 MSPS (default settings)  
Noise density = −153 dBFS/Hz at 500 MSPS  
1.25 V, 2.50 V, and 3.3 V dc supply operation  
Flexible input range  
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)  
95 dB channel isolation/crosstalk  
Amplitude detect bits for efficient automatic gain control  
(AGC) implementation  
Noise shaping requantizer (NSR) option for main receiver  
function  
Variable dynamic range (VDR) option for digital  
predistortion (DPD) function  
2 integrated wideband digital processors per channel  
12-bit numerically controlled oscillator (NCO), up to  
4 cascaded half-band filters  
GENERAL DESCRIPTION  
The AD6679 is a 135 MHz bandwidth mixed-signal intermediate  
frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS  
analog-to-digital converters (ADCs) and various digital signal  
processing blocks consisting of four wideband DDCs, an NSR,  
and VDR monitoring. It has an on-chip buffer and a sample-and-  
hold circuit designed for low power, small size, and ease of use.  
This product is designed to support communications applications  
capable of sampling wide bandwidth analog signals of up to 2 GHz.  
The AD6679 is optimized for wide input bandwidth, high sampling  
rates, excellent linearity, and low power in a small package.  
The dual ADC cores feature a multistage, differential pipelined  
architecture with integrated output error correction logic. Each  
ADC features wide bandwidth inputs supporting a variety of  
user-selectable input ranges. An integrated voltage reference  
eases design considerations.  
Differential clock inputs  
Integer clock divide by 1, 2, 4, or 8  
Energy saving power-down modes  
Small signal dither  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1  
(1.25V)  
AVDD2  
(2.50V)  
AVDD3  
(3.3V)  
DVDD  
(1.25V)  
DRVDD  
(1.25V)  
SPIVDD  
(1.22V TO 3.4V)  
BUFFER  
VIN+A  
VIN–A  
FD_A  
D0±  
SIGNAL PROCESSING  
ADC  
D1±  
D2±  
D3±  
DIGITAL DOWN-  
CONVERSION  
(×4)  
D4±  
D5±  
16  
D6±  
D7±  
FAST  
DETECT  
SIGNAL  
MONITOR  
LVDS  
OUTPUT  
STAGING  
D8±  
DATA  
ROUTER  
MUX  
LVDS  
OUTPUTS  
D9±  
NOISE SHAPING  
REQUANTIZER  
(×2)  
FD_B  
V_1P0  
VIN+B  
VIN–B  
D10±  
D11±  
D12±  
D13±  
DCO±  
STATUS±  
BUFFER  
VARIABLE  
DYNAMIC RANGE  
(×2)  
ADC  
FAST  
DETECT  
CLOCK  
GENERATION  
AND ADJUST  
CLK+  
CLK–  
AD6679  
÷2  
÷4  
÷8  
SIGNAL  
MONITOR  
PDWN/STBY  
SPI CONTROL  
DGND  
AGND  
SDIO  
DRGND  
SYNC±  
SCLK  
CSB  
Figure 1.  
Rev. B  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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