AD6624
Table XIII. Memory Map for Input Port Control Registers
Ch Address
Register
Bit Width
Comments
00
01
02
03
Lower Threshold A
Upper Threshold A
Dwell Time A
10
10
20
5
9–0:
9–0:
19–0:
4:
Lower Threshold for Input A
Upper Threshold for Input A
Minimum Time below Lower Threshold A
Output Polarity LIA-A and LIA-B
Interleaved Channels
Gain Range A Control Register
3:
2–0:
9–0:
9–0:
19–0:
4:
Linearization Hold-Off Register
Lower Threshold for Input B
Upper Threshold for Input B
Minimum Time below Lower Threshold B
Output Polarity LIB-A and LIB-B
Interleaved Channels
04
05
06
07
Lower Threshold B
Upper Threshold B
Dwell Time B
10
10
20
5
Gain Range B Control Register
3:
2–0:
Linearization Hold-Off Register
External Memory Map
Bits 6 and 7 facilitate verification of a given filter design and in
conjunction with the MISR registers, allow for detailed in-system
chip testing. In conjunction with the JTAG test board, very high
levels of chip verification can be done during system test, in both
the factory and field.
When broadcast is enabled (Bit 6 set high), readback is not valid
because of the potential for internal bus contention. Therefore,
if readback is subsequently desired, the broadcast bit should
be set low.
Bits 1–0 of this register are address bits that decode which of the
four channels are being accessed. If the Instruction bits decode
an access to multiple channels, these bits are ignored. If the
Instruction decodes an access to a subset of chips, the A[9:8] bits
will otherwise determine the channel being accessed.
PIN_SYNC Control Register
External Address [4] is the PIN_SYNC control register and is
write only.
Bits 0–3 of this register are the SYNC_EN control bits. These
pins may be written to by the controller to allow pin synchroni-
zation of a selected channel. Although there are four inputs,
these do not necessarily go to the channel of the same number.
This is fully configurable at the channel level as to which bit to
look at. All four channels may be configured to synchronize
from a single position, or they may be paired or all independent.
Channel Address Register (CAR)
This register represents the 8-bit internal address of each channel.
If the autoincrement bit of the ACR is 1, this value will be incre-
mented after every access to the DR0 register, which will in
turn access the location pointed to by this address. The Channel
Address register cannot be read back while the broadcast bit
is set high.
Bit 4 determines if the synchronization is to apply to a
chip start. If this bit is set, a chip start will be initiated
PIN_SYNC occurs.
SOFT_SYNC Control Register
External Address [5] is the SOFT_SYNC control register and is
write only.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, the NCO Frequency will be updated when the
PIN_SYNC occurs.
Bits 0–3 of this register are the SOFT_SYNC control bits. These
pins may be written to by the controller to initiate the synchro-
nization of a selected channel. Although there are four inputs,
these do not necessarily go to the channel of the same number.
This is fully configurable at the channel level as to which bit to
look at. All four channels may be configured to synchronize from a
single position, or they may be paired or all independent.
Bit 6 is used to ignore repetitive synchronization signals. In
some applications, this signal may occur periodically. If this bit
is clear, each PIN_SYNC will restart/hop the channel. If this bit
is set, only the first occurrence will cause the chip to take action.
Bit 7 is used with Bits 6 and 7 of external address 5. When this
bit is cleared, the data supplied to the internal databus simulates
a normal ADC. When this bit is set, the data supplied is in the
form of a time-multiplexed ADC such as the AD6600 (this
allows the equivalent of testing in the 4-channel input mode).
Internally, when set, this bit forces the IEN pin to toggle as if it
were driven by the A/B signal of the AD6600.
Bit 4 determines if the synchronization is to apply to a chip
start. If this bit is set, a chip start will be initiated.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, the NCO frequency will be updated when the
SOFT_SYNC occurs.
Bit 6 configures how the internal databus is configured. If this
bit is set low, the internal ADC databuses are configured nor-
mally. If this bit is set, the internal test signals are selected. The
internal test signals are configured in Bit 7 of this register.
SLEEP Control Register
External Address [3] is the sleep register.
Bits 3–0 control the state of each of the channels. Each bit corre-
sponds to one of the possible RSP channels within the device. If
this bit is cleared, the channel operates normally. However,
when this bit is set, the indicated channel enters a low-power
sleep mode.
Bit 7 if set clear, a negative full-scale signal is generated and
made available to the internal databus. If this bit is high, inter-
nal pseudo-random sequence generator is enabled and this data
is available to the internal databus. The combined functions of
–34–
REV. B
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