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AD6402 PDF预览

AD6402

更新时间: 2024-02-04 01:29:42
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
8页 113K
描述
IF Transceiver Subsystem

AD6402 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-28
针数:28Reach Compliance Code:unknown
ECCN代码:5A991.GHTS代码:8542.39.00.01
风险等级:5.83JESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:10.21 mm
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-25 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.85,3.1/4.5 V认证状态:Not Qualified
座面最大高度:1.73 mm子类别:Other Telecom ICs
表面贴装:YES技术:BIPOLAR
电信集成电路类型:TELECOM CIRCUIT温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm

AD6402 数据手册

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AD6402  
VCO  
VCOGND  
1.2k  
8pF  
47pF  
V
TUNE  
39nH  
AD6402  
1nF  
SMV  
1204-37  
SMV  
1204-36  
4.7nF  
330Ω  
330Ω  
1nF  
1nF  
FMMOD2  
FMMOD1  
TXOUT  
TXOUTB  
330Ω  
TXMOD  
TXIF+  
100pF  
240Ω  
180pF  
TXIF–  
MODOUT  
150pF  
VCCI  
Figure 1.  
O VERVIEW  
equal to the sum of the IF frequency plus the frequency of the  
PLL demodulator input as defined by the reference clock  
divider ratios.  
T he AD6402 forms the basis of a highly integrated RF trans-  
ceiver with the benefits of increased sensitivity and wide dy-  
namic range that a dual-conversion architecture provides. T he  
IC contains a low dropout voltage regulator to isolate the IF and  
demodulator VCOs from variation in the battery voltage, such  
as power-supply transients caused by the PA. T he AD6402 also  
provides control circuitry that allows subcircuits to be turned off  
and on as necessary to minimize power consumption.  
T he transmit IF VCO uses an external tank circuit. T his signal  
is upconverted to the transmit frequency in the RF mixer sec-  
tion of the radio. Using a transmit IF VCO prevents two prob-  
lems: feedback from the PA at the RF frequency does not cause  
distortion in the modulating circuit because the frequencies are  
widely separated and the IF tank circuit can be optimized for  
modulation linearity.  
O per ation D ur ing Receive  
T he AD6402 contains the second mixer, integrated second-IF  
bandpass filter, logarithmic-limiting amplifier, and PLL de-  
modulator. A SAW IF bandpass filter is usually required at the  
IF input in order to provide channel selectivity.  
T he output of the transmit VCO passes through buffer amplifier  
and leaves the AD6402 via an optional LC filter between the RF  
and IF ICs. T he output of the LC filter may then be fed to a  
transmit upconversion mixer for conversion to the final RF  
frequency.  
T he placement of the SAW filter in the signal path between  
the AD6402 and the RF section and the partitioning of the  
receiver’s RF and IF receive circuits minimizes the leakage  
around the SAW filter and maximizes the RF to IF isolation.  
O nboar d Voltage Regulation  
T he AD6402 contains a low dropout voltage regulator to spe-  
cifically isolate the VCOs and synthesizer from the voltage  
“kick” that occurs when a power amplifier switches on and the  
battery voltage abruptly drops. T he AD6402 uses an integral  
vertical PNP pass transistor.  
T he output of the SAW filter enters the AD6402 via the second  
downconversion mixer. T his mixer is a high gain, doubly-  
balanced Gilbert-cell type. T he mixer downconverts the signal  
to the second IF, which is 1.5 × or 2.5 × the reference frequency.  
T his multiple is determined by the state of the REFSEL pin. An  
on-chip two section bandpass filter provides additional selectiv-  
ity to provide attenuation of adjacent channels. T he VCO con-  
trol voltage output of the PLL demodulator tunes this filter to  
the second IF.  
T he regulator in the AD6402 IF IC supplies the voltage for the  
VCOs on both the RF section and AD6402. T he other sections  
of the AD6402 should be powered from an independently regu-  
lated source at 2.85 V. Since the VCOs are isolated from this  
source, possible problems due to VCO supply pushing are con-  
siderably reduced.  
T he bandpass filter’s output enters a successive-detection loga-  
rithmic-limiting IF amplifier. T he RSSI detectors are distrib-  
uted across the entire IF strip, including the mixer, and provide  
80 dB RSSI range. T he IF strip’s limiting gain also exceeds 80  
dB. T he RSSI signal is low-pass filtered and proceeds off-chip  
to the baseband subsystem. T he limited output of the logarith-  
mic amplifier enters a PLL demodulator, which provides de-  
modulation of the received signal. T he PLL uses an integrated  
VCO with no external components.  
Fr equency Contr ol  
T he AD6402 requires an external synthesizer to provide the  
control voltages for the tank circuit of the IF VCO. Normally  
this will be the IF section of a dual synthesizer controlling both  
IF and RF frequency generation.  
It is recommended that the VCO on the RF section implement  
the channel selection on transmit and receive; the VCO on the  
AD6402 may therefore operate at a fixed frequency. T his ac-  
complishes two goals: first, the IF VCO being modulated can be  
optimized for modulation linearity and the RF VCO can be  
optimized for tuning range, and second, feedback from the PA  
at will not couple into the modulating circuit to cause spurious  
responses.  
O per ation D ur ing Tr ansm it  
T he transmit signal path consists of a low-pass filter that can be  
user configured for antialiasing of a baseband transmit signal.  
An IF VCO, which should be tuned to a frequency equal to the  
receive IF frequency plus the desired demodulator input fre-  
quency, may be open-loop modulated by the transmit signal for  
FM and FSK schemes. T he receive IF mixer uses high side  
mixing and therefore the IF VCO should be set to a frequency  
All key sections of the AD6402 may be powered up or down as  
necessary to minimize power consumption and maximize  
battery life.  
–4–  
REV. 0  

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