AD6402
RECO MMEND ED O P ERATING CO ND ITIO NS
P IN CO NFIGURATIO N
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 V–4.5 V
IFVCC1, IFVCC2, PLLVCC . . . . . . . . . . . . . . . . . . . .2.85 V
Operating T emperature Range . . . . . . . . . . . –25°C to +85°C
1
2
28 TXOUT
TXOUTB
MODOUT
FMMOD2
FMMOD1
VCOGND
VCO
ABSO LUTE MAXIMUM RATINGS*
27 REFSEL
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature, Soldering (60 sec) . . . . . . . . . . . . +300°C
3
26
IFVCC1
4
25 IFIN
5
24 IFGND
AD6402
TOP VIEW
6
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.
23
22
21
20
19
18
17
16
15
RSSI
(Not to Scale)
VREG
7
IFVCC2
PLLGND
8
VBAT
CTL3
CTL2
9
PLLVCC
SLREF
DOUT
10
11
12
13
14
T hermal Characteristics:
28-lead SSOP package: θJA = 109°C/W.
CTL1
CFILT
COFF
REXT
DFILP
PLLOUT
REFIN
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
Model
AD6402ARS
AD6402ARS-REEL
–25°C to +85°C
–25°C to +85°C
28-Lead SSOP
28-Lead SSOP
P IN FUNCTIO N D ESCRIP TIO NS
P in
Mnem onic
Function
1
2
3
4
5
6
7
T XOUT B
MODOUT
FMMOD2
FMMOD1
VCOGND
VCO
T ransmit IF VCO Buffer Inverting Output
Frequency Modulator Filter Op Amp Output
Frequency Modulator Filter Op Amp Noninverting input
Frequency Modulator Filter Op Amp Inverting input
IF VCO Ground
IF VCO T ank Connection
Regulated Supply Output for RF VCO (Supplies Internal IF VCO, Mode Control, Bandgap Reference,
and COFF Buffer)
VREG
8
9
VBAT
CT L3
CT L2
CT L1
CFILT
COFF
REXT
REFIN
PLLOUT
DFILP
DOUT
SLREF
PLLVCC
PLLGND
IFVCC2
RSSI
IFGND
IFIN
IFVCC1
REFSEL
T XOUT
Battery Supply Voltage Input to Internal Regulator and COFF Charge Pump
Mode Control Input 3, CMOS Logical Level
Mode Control Input 2, CMOS Logical Level
Mode Control Input 1, CMOS Logical Level
PLL Demodulator Loop Filter Capacitor
PLL Demodulator Frequency Offset Voltage T rack/Hold Capacitor
External Current-Setting Resistor
Baseband Reference Frequency Input, 100 mV p-p, AC Coupled
PLL Demodulator Output
Data Filter Voltage-Follower Input
Data Filter Voltage-Follower Output
PLL Demodulator Output DC Reference Voltage
PLL Demodulator and Data Filter Supply Input
PLL Demodulator and Data Filter Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IF Limiter Supply Input 1
RSSI Output
IF Stage, Mixer, Band Pass Filter, IF VCO Buffer, T x Op Amp, Mode Control, and Regulator Ground
IF Mixer Input, ZO = 150 Z
IF Mixer, Limiter 1, IF Filter, IF VCO Buffer
Reference Frequency Select; IF = 1.5× or 2.5× Reference Frequency, CMOS Logical Level Input
T ransmit IF VCO Buffer Output
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6402 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–