AD626AR-REEL

更新时间： 2024-02-02 08:33:25

品牌	Logo	应用领域
亚德诺 - ADI		放大器
页数	文件大小	规格书
12页	169K
描述
Low Cost, Single Supply Differential Amplifier

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数据手册

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AD626AR-REEL 数据手册

AD626

ERROR

OUT

10k⍀

100

2k⍀

10k⍀

INPUT

20V p–p

AD626

1k⍀

–V

Figure 27. Settling Time Test Circuit

THEORY OF OPERATION

Figure 25. Settling Time. V_S= +5 V, G = 10

The AD626 is a differential amplifier consisting of a precision

balanced attenuator, a very low drift preamplifier (A1), and an

output buffer amplifier (A2). It has been designed so that small

differential signals can be accurately amplified and filtered in the

presence of large common-mode voltages (V_CM), without the

use of any other active components.

100

Figure 28 shows the main elements of the AD626. The signal

inputs at Pins 1 and 8 are first applied to dual resistive attenuators

R1 through R4 whose purpose is to reduce the peak common-

mode voltage at the input to the preamplifier—a feedback stage

based on the very low drift op amp A1. This allows the differen-

tial input voltage to be accurately amplified in the presence of

large common-mode voltages six times greater than that which

can be tolerated by the actual input to A1. As a result, the input

CMR extends to six times the quantity (V_S– 1 V). The overall

common-mode error is minimized by precise laser-trimming of

R3 and R4, thus giving the AD626 a common-mode rejection

ratio (CMRR) of at least 10,000:1 (80 dB).

Figure 26. Settling Time. V_S= +5 V, G = 100

To minimize the effect of spurious RF signals at the inputs due

to rectification at the input to A1, small filter capacitors C1 and

C2 are included.

FILTER

5pF

AD626

200k⍀

R12

100k⍀

+IN

–IN

OUT

200k⍀

5pF

R17

95k⍀

41k⍀

R15

10k⍀

4.2k⍀

500⍀

R10

10k⍀

R13

10k⍀

R14

555⍀

R11

10k⍀

500⍀

GAIN = 100

–V

GND

Figure 28. Simplified Schematic

REV. C

–9–

1...6 7 8910 11 12

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