AD598A

更新时间： 2024-02-05 03:07:15

品牌	Logo	应用领域
亚德诺 - ADI		调节器
页数	文件大小	规格书
16页	555K
描述
LVDT Signal Conditioner

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技术参数
数据手册

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AD598A 技术参数

Source Url Status Check Date：	2013-05-01 14:56:15.092	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	PLASTIC, SOIC-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	8.76	Is Samacsys：	N
最大模拟输入电压：	3.5 V	转换器类型：	SIGNAL CONDITIONER
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e0
长度：	12.8 mm	湿度敏感等级：	3
标称负供电电压：	-15 V	功能数量：	1
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	电源：	+-15 V
认证状态：	Not Qualified	座面最大高度：	2.65 mm
信号/输出频率：	20000 Hz	子类别：	Position Converters
最大压摆率：	16 mA	最大供电电压：	36 V
最小供电电压：	13 V	标称供电电压：	15 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.5 mm	Base Number Matches：	1

AD598A 数据手册

AD598

a voltage proportional to position. This technique uses the pri-

mary excitation voltage as a phase reference to determine the

polarity of the output voltage. There are a number of problems

associated with this technique such as (1) producing a constant

amplitude, constant frequency excitation signal, (2) compensating

for LVDT primary to secondary phase shifts, and (3) compen-

sating for these shifts as a function of temperature and frequency.

As shown in Figure 6, the input to the integrator is [(A+B)d]B.

Since the integrator input is forced to 0, the duty cycle d =

B/(A+B).

The output comparator which produces d = B/(A+B) also con-

trols an output amplifier driven by a reference current. Duty

cycle signals d and (1–d) perform separate modulations on the

reference current as shown in Figure 6, which are summed. The

summed current, which is the output current, is I_REF× (1–2d).

The AD598 eliminates all of these problems. The AD598 does

not require a constant amplitude because it works on the ratio of

the difference and sum of the LVDT output signals. A constant

frequency signal is not necessary because the inputs are rectified

and only the sine wave carrier magnitude is processed. There is

no sensitivity to phase shift between the primary excitation and

the LVDT outputs because synchronous detection is not em-

ployed. The ratiometric principle upon which the AD598 oper-

ates requires that the sum of the LVDT secondary voltages

remains constant with LVDT stroke length. Although LVDT

manufacturers generally do not specify the relationship between

V_A+V_Band stroke length, it is recognized that some LVDTs do

not meet this requirement. In these cases a nonlinearity will

result. However, the majority of available LVDTs do in fact

meet these requirements.

Since d = B/(A+B), by substitution the output current equals

_REF× (A–B)/(A+B). This output current is then filtered and

converted to a voltage since it is forced to flow through the scal-

ing resistor R2 such that:

V_OUT= I_REF×( A – B)/(A + B)× R2

CONNECTING THE AD598

The AD598 can easily be connected for dual or single supply

operation as shown in Figures 7 and 12. The following general

design procedures demonstrate how external component values

are selected and can be used for any LVDT which meets AD598

input/output criteria.

Parameters which are set with external passive components in-

clude: excitation frequency and amplitude, AD598 system

bandwidth, and the scale factor (V/inch). Additionally, there are

optional features, offset null adjustment, filtering, and signal in-

tegration which can be used by adding external components.

The AD598 utilizes a special decoder circuit. Referring to the

block diagram and Figure 6 below, an implicit analog comput-

ing loop is employed. After rectification, the A and B signals are

multiplied by complementary duty cycle signals, d and (I–d)

respectively. The difference of these processed signals is inte-

grated and sampled by a comparator. It is the output of this

comparator that defines the original duty cycle, d, which is fed

back to the multipliers.

V TO I

INPUT

FILT

BINARY SIGNAL

d - DUTY CYCLE

0<d<1

COMP

±1

∑

INTEG

COMP

V TO I

(A+B) d–B

INPUT

FILT

1–d

^●A+B

COMP

±1

VOLTS

OUTPUT

A–B

I_REF

^●A+B

I_REF

BANDGAP

REFERENCE

∑

FILT

INTEG

V TO I

RTO

OFFSET

A–B

A+B

V_OUT

= R_SCALEx I _REF

Figure 6. Block Diagram of Decoder

–5–

REV. A

1 2 3 456 7 8...16

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