Tiny 16-/14-/12-Bit SPI nanoDAC+, with
2 (16-Bit) LSB INL and 2 ppm/°C Reference
AD5683R/AD5682R/AD5681R/AD5683
FUNCTIONAL BLOCK DIAGRAM
Data Sheet
FEATURES
V
*
V
V
DD
LOGIC
REF
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): 2 LSB maximum at 16 bits
AD5683R/AD5682R/AD5681R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5683
POWER-ON
RESET
AD5683R/
AD5682R/
AD5681R
2.5V
REF
LDAC
REF
DAC
REGISTER
OUTPUT
BUFFER
V
16-/14-/12-BIT
DAC
OUT
RESET
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.05% of FSR maximum
Low glitch: 0.1 nV-sec
INPUT
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
CONTROL LOGIC
*NOT AVAILABLE IN ALL THE MODELS
GND
SYNC SCLK SDI SDO*
High drive capability: 20 mA
Figure 1. AD5683R/AD5682R/AD5681R MSOP
Low power: 1.2 mW at 3.3 V
(For more information, see the Functional Block Diagrams—LFCSP section.)
Independent logic supply: 1.62 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
GENERAL DESCRIPTION
Table 1. Single-Channel nanoDAC+ Portfolio
The AD5683R/AD5682R/AD5681R/AD5683, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage out digital-to-analog converters (DACs). The
devices, except the AD5683, include an enabled by default internal
2.5 V reference, offering 2 ppm/°C drift. The output span can be
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in a 2.00 mm ×
2.00 mm, 8-lead LFCSP or a 10-lead MSOP.
Interface
Reference
Internal
External
Internal
External
16-Bit
14-Bit
12-Bit
SPI
AD5683R
AD5683
AD5693R
AD5693
AD5682R
AD5681R
I2C
AD5692R
AD5691R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5683R/AD5683 (16-bit): 2 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient.
5 ppm/°C maximum temperature coefficient.
3. Two Package Options.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The AD5683R/AD5682R
/AD5681R/AD5683 contain a power-down mode that reduces
the current consumption of the device to 2 µA (maximum) at 5 V
and provides software selectable output loads while in power-
down mode.
2.00 mm × 2.00 mm, 8-lead LFCSP.
10-lead MSOP.
The AD5683R/AD5682R/AD5681R/AD5683 use a versatile
3-wire serial interface that operates at clock rates of up to 50 MHz.
RESET
Some devices also include asynchronous
pin options, allowing 1.8 V compatibility.
pin and VLOGIC
Rev. D
Document Feedback
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Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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