Datasheet > AD5541_12

AD5541_12

更新时间： 2022-04-12 00:22:01

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	382K
描述
2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs

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AD5541_12 数据手册

AD5541/AD5542

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OUT

AD5541

AGND

REF

DGND

DIN

TOP VIEW

(Not to Scale)

SCLK

Figure 4. AD5541 Pin Configuration

Table 5. AD5541 Pin Function Descriptions

Pin No. Mnemonic Description

V_OUT

AGND

REF

Analog Output Voltage from the DAC.

Ground Reference Point for Analog Circuitry.

Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V_DD

Logic Input Signal. The chip select signal is used to frame the serial data input.

SCLK

DIN

DGND

V_DD

Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.

Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.

Digital Ground. Ground reference for digital circuitry.

Analog Supply Voltage, 5 V 10%.

RFB

14 V

13 INV

OUT

AGNDF

12 DGND

11 LDAC

10 DIN

AD5542

TOP VIEW

(Not to Scale)

AGNDS

REFS

REFF

SCLK

NC = NO CONNECT

Figure 5. AD5542 Pin Configuration

Table 6. AD5542 Pin Function Descriptions

Pin No. Mnemonic Description

RFB

V_OUT

Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.

Analog Output Voltage from the DAC.

AGNDF

AGNDS

REFS

REFF

Ground Reference Point for Analog Circuitry (Force).

Ground Reference Point for Analog Circuitry (Sense).

Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V_DD

Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V_DD

Logic Input Signal. The chip select signal is used to frame the serial data input.

SCLK

Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.

No Connect.

DIN

LDAC

Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.

LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the

input register.

DGND

INV

Digital Ground. Ground reference for digital circuitry.

Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in

bipolar mode.

V_DD

Analog Supply Voltage, 5 V 10%.

Rev. F | Page 6 of 20

1...3 4 567 8 9...20

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