AD5346/AD5347/AD5348
5V
DECODING MULTIPLE AD5346/AD5347/AD5348s
0.1µF
10µF
1kΩ
1kΩ
V
IN
FAIL
PASS
CS
The
decode a number of DACs. In this application, all DACs in the
WR CS
to
pin on these devices can be used in applications to
V
DD
V
V
AB
REF
REF
V
A
OUT
system receive the same data and
one of the DACs will be active at any one time, so data will only
CS
pulses, but only the
PASS/
FAIL
1/2
CMP04
AD5346/AD5347/
AD5348
be written to the DAC whose
is low.
V
B
OUT
1/6 74HC05
GND
The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state.
Figure 44 shows a diagram of a typical setup for decoding
multiple devices in a system. Once data has been written
sequentially to all DACs in a system, all the DACs can be
Figure 45. Programmable Window Detector
PROGRAMMABLE CURRENT SOURCE
Figure 46 shows the AD5346/AD5347/AD5348 used as the
control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output
voltage from the DAC is applied across the current setting
resistor of 4.7 kΩ in series with the 470 Ω adjustment
potentiometer, which gives an adjustment of about 5%.
Suitable transistors to place in the feedback loop of the ampli-
fier include the BC107 and the 2N3904, which enable the
current source to operate from a minimum VSOURCE of 6 V. The
operating range is determined by the operating characteristics
of the transistor. Suitable amplifiers include the AD820 and the
OP295, both having rail-to-rail operation on their outputs. The
current for any digital input code and resistor value can be
calculated as follows:
LDAC
updated simultaneously using a common
line. A com-
CLR
mon
line can also be used to reset all DAC outputs to 0 V.
AD5346/AD5347
A0
/AD5348
A0
A1
A2
A1
A2
WR
LDAC
CLR
WR
LDAC
CLR
CS
DATA
INPUTS
AD5346/AD5347
/AD5348
A0
A1
A2
WR
DATA
LDAC
CLR
CS
INPUTS
V
DD
D
I = G ×VREF (2N × R)
mA
V
CC
1G
1A
1B
AD5346/AD5347
1Y0
1Y1
1Y2
ENABLE
CODED
/AD5348
A0
A1
A2
where:
74HC139
DGND
ADDRESS
WR
LDAC
CLR
CS
DATA
INPUTS
1Y3
G is the gain of the buffer amplifier (1 or 2).
D is the digital input code.
N is the DAC resolution (8, 10, or 12 bits).
R is the sum of the resistor plus adjustment potentiometer in kΩ.
AD5346/AD5347
/AD5348
A0
A1
A2
WR
LDAC
CLR
CS
DATA
INPUTS
V
= 5V
DD
0.1µF
0.1µF
10µF
Figure 44. Decoding Multiple DAC Devices
V
SOURCE
AD5346/AD5347/AD5348 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
V
IN
5V
LOAD
V
DD
EXT
REF
V
V
*
V
*
OUT
OUT
REF
A digitally programmable upper/lower limit detector using two
of the DACs in the AD5346/AD5347/AD5348 is shown in
Figure 45. Any pair of DACs in the device may be used, but for
simplicity the description refers to DACs A and B.
AD5346/AD5347/
AD5348
GND
4.7kΩ
470Ω
The upper and lower limits for the test are loaded to DACs A
and B which, in turn, set the limits on the CMP04. If a signal at
the VIN input is not within the programmed window, an LED
indicates the fail condition.
GND
*ONLY ONE CHANNEL OF V
AND V
SHOWN
REF
OUT
Figure 46. Programmable Current Source
Rev. 0 | Page 20 of 24
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