Datasheet > AD5337_15

AD5337_15

更新时间： 2022-02-26 12:08:16

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	593K
描述
2.5 V to 5.5 V, 250A, 2-Wire Interface, Dual Voltage Output, 8-/10-/12-Bit DACs

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数据手册

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AD5337_15 数据手册

AD5337/AD5338/AD5339

A Grade¹

Typ

B Grade¹

Typ

Parameter²

LOGIC INPUTS (A±)⁵

Min

Max

Min

Max

Unit

Conditions/Comments

Input Current

Input Low Voltage (V_IL)

±ꢀ

±.8

±.1

±.5

±ꢀ

±.8

±.1

±.5

μA

V_DD= 5 V ± ꢀ±%

V_DD= 3 V ± ꢀ±%

V_DD= 2.5 V

Input High Voltage (V_IH)

2.4

2.ꢀ

2.±

2.4

2.ꢀ

2.±

V_DD= 5 V ± ꢀ±%

V_DD= 3 V ± ꢀ±%

V_DD= 2.5 V

Pin Capacitance

LOGIC INPUTS (SCL, SDA)⁵

Input High Voltage (V_IH)

±.7 ×

V_DD

−±.3

V_DD

±.3

+±.3

V_DD

±.7 ×

V_DD

–±.3

V_DD

±.3

+±.3

V_DD

SMBus compatible at

V_DD< 3.1 V

SMBus compatible at

Input Low Voltage (V_IL)

_DD< 3.1 V

Input Leakage Current (I_IN)

±ꢀ

μA

Input Hysteresis (V_HYST

)

±.±5 ×

V_DD

±.±5 ×

V_DD

Input Capacitance (C_IN)

Glitch Rejection

5±

Input filtering suppresses

noise spikes of less than

5± ns

LOGIC OUTPUT (SDA)⁵

Output Low Voltage (V_OL)

±.4

±.1

±ꢀ

±.4

±.1

±ꢀ

μA

I_SINK= 3 mA

I_SINK= 1 mA

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

V_DD

I_DD(Normal Mode)⁷

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.1 V

I_DD(Power-Down Mode)

V_DD= 4.5 V to 5.5 V

2.5

5.5

2.5

5.5

V_IH= V_DDand V_IL= GND

I_DD= 4 μA (max) during ±

readback on SDA

3±±

25±

375

35±

3±±

25±

375

35±

μA

±.2

ꢀ.±

±.2

ꢀ.±

μA

V_DD= 2.5 V to 3.1 V

±.±8

ꢀ.±±

±.±8

ꢀ.±±

I_DD= ꢀ.5 μA (max) during ±

readback on SDA

^ꢀTemperature range for A Version and B Version: −4±°C to +ꢀ±5°C; typical at 25°C.

²See the Terminology section for explanations of the specific parameters.

³DC specifications tested with the outputs unloaded.

⁴Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-ꢀ (Code 28 to Code 995), AD5339 (Code ꢀꢀ5 to Code 398ꢀ).

⁵Guaranteed by design and characterization; not production tested.

¹For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V_REF= V_DDand offset plus gain error must be positive.

⁷I_DDspecification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.

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