AD5303/AD5313/AD5323
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
2
CLR
Active low control input that loads all zeroes to both input and DAC registers.
LDAC
Active low control input that transfers the contents of the input registers to their respective DAC
registers. Pulsing this pin low allows either or both DAC registers to be updated if the input regis-
ters have new data. This allows simultaneous update of both DAC outputs
3
4
VDD
Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be
decoupled to GND.
V
V
V
REFB
REFA
OUTA
Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buff-
ered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from
0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
5
Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a
buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range
from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
6
7
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
BUF A
BUF B
DCEN
PD
Control pin that controls whether the reference input for DAC A is unbuffered or buffered. If this
pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.
8
Control pin that controls whether the reference input for DAC B is unbuffered or buffered. If this
pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.
9
This pin is used to enable the daisy-chaining option. This should be tied high if the part is being
used in a daisy-chain. The pin should be tied low if it is being used in stand-alone mode.
10
Active low control input that acts as a hardware power-down option. This pin overrides any soft-
ware power-down option. Both DACs go into power-down mode when this pin is tied low. The
DAC outputs go into a high impedance state and the current consumption of the part drops to
200 nA @ 5 V (50 nA @ 3 V).
11
12
V
OUTB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers-on the SCLK and DIN buffers and enables the input shift register. Data
is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the
16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the device.
13
14
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered-down
after each write cycle.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input. The DIN input buffer is powered-down after each write cycle.
15
16
GND
SDO
Ground reference point for all circuitry on the part.
Serial Data Output that can be used for daisy-chaining a number of these devices together or for
reading back the data in the shift register for diagnostic purposes. The serial data output is valid on
the falling edge of the clock.
TERMINOLOGY
RELATIVE ACCURACY
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 5.
amplifier. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of 1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design. A
typical DNL vs. code plot can be seen in Figure 8.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
–6–
REV. 0
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