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AD5322ARM PDF预览

AD5322ARM

更新时间: 2024-01-17 01:49:13
品牌 Logo 应用领域
亚德诺 - ADI 转换器光电二极管
页数 文件大小 规格书
24页 1044K
描述
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs

AD5322ARM 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP10,.19,20针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.25
最大模拟输出电压:5.499 V最小模拟输出电压:0.001 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:S-PDSO-G10
JESD-609代码:e3长度:3 mm
最大线性误差 (EL):0.1953%湿度敏感等级:1
位数:12功能数量:1
端子数量:10最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP10,.19,20
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/5.5 V
认证状态:Not Qualified座面最大高度:1.1 mm
最大稳定时间:10 µs标称安定时间 (tstl):8 µs
子类别:Other Converters最大压摆率:0.45 mA
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

AD5322ARM 数据手册

 浏览型号AD5322ARM的Datasheet PDF文件第1页浏览型号AD5322ARM的Datasheet PDF文件第2页浏览型号AD5322ARM的Datasheet PDF文件第3页浏览型号AD5322ARM的Datasheet PDF文件第5页浏览型号AD5322ARM的Datasheet PDF文件第6页浏览型号AD5322ARM的Datasheet PDF文件第7页 
AD5302/AD5312/AD5322  
A Version1  
B Version1  
Typ  
Parameter2  
Min  
Typ  
Max  
Min  
Max  
Unit  
Test Conditions/Comments  
POWER REQUIREMENTS  
VDD  
IDD (Normal Mode)  
VDD = 4.5 V to 5.5 V  
VDD = 2.5 V to 3.ꢀ V  
2.5  
5.5  
2.5  
5.5  
V
IDD specification is valid for all DAC codes  
Both DACs active and excluding load currents  
Both DACs in unbuffered mode, VIH = VDD and  
300  
230  
450  
350  
300  
230  
450  
350  
μA  
μA  
VIL = GND; in buffered mode, extra current is  
typically × ꢁA per DAC where x = 5 ꢁA + VREF/RDAC  
IDD (Full Power-Down)  
VDD = 4.5 V to 5.5 V  
VDD = 2.5 V to 3.ꢀ V  
0.2  
0.05  
1
1
0.2  
0.05  
1
1
μA  
μA  
1 Temperature range: A, B version: –40°C to +105°C.  
2 See Terminology section.  
3 DC specifications tested with the outputs unloaded.  
4 Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).  
5 Guaranteed by design and characterization, not production tested.  
In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage,  
VREF = VDD and offset plus gain error must be positive.  
AC SPECIFICATIONS  
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1  
Table 2.  
A, B Version2  
Parameter3  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
Output Voltage Settling Time  
AD5302  
AD5312  
VREF = VDD = 5 V  
7
8
8
9
10  
μs  
μs  
μs  
¼ Scale to ¾ Scale Change (0 × 40 to 0 × C0)  
¼ Scale to ¾ Scale Change (0 × 100 to 0 × C300)  
¼ Scale to ¾ Scale Change (0 × 400 to 0 × C00)  
AD5322  
Slew Rate  
0.7  
12  
V/μs  
nV-s  
nV-s  
nV-s  
nV-s  
kHz  
dB  
Major-Code Transition Glitch Energy  
Digital Feedthrough  
Analog Crosstalk  
DAC-to-DAC Crosstalk  
Multiplying Bandwidth  
Total Harmonic Distortion  
1 LSB Change Around Major Carry (011…11 to 100…00)  
0.10  
0.01  
0.01  
200  
−70  
VREF = 2 V 0.1 V p-p, Unbuffered Mode  
VREF = 2.5 V 0.1 V p-p, Frequency = 10 kHz  
1 Guaranteed by design and characterization, not production tested.  
2 Temperature range: A, B version: −40°C to +105°C.  
3 See Terminology section.  
Rev. D | Page 4 of 24  
 
 
 
 

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