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AD5321BRMZ1 PDF预览

AD5321BRMZ1

更新时间: 2024-02-20 19:10:00
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
24页 429K
描述
2.5 V to 5.5 V, 120 μA, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs

AD5321BRMZ1 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:MSOP-8Reach Compliance Code:compliant
风险等级:5.82Is Samacsys:N
最大模拟输出电压:5.499 V最小模拟输出电压:0.001 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:S-PDSO-G8
长度:3 mm最大线性误差 (EL):0.3906%
位数:12功能数量:1
端子数量:8最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
座面最大高度:1.1 mm最大稳定时间:10 µs
标称安定时间 (tstl):8 µs最大压摆率:0.225 mA
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:3 mm
Base Number Matches:1

AD5321BRMZ1 数据手册

 浏览型号AD5321BRMZ1的Datasheet PDF文件第2页浏览型号AD5321BRMZ1的Datasheet PDF文件第3页浏览型号AD5321BRMZ1的Datasheet PDF文件第4页浏览型号AD5321BRMZ1的Datasheet PDF文件第6页浏览型号AD5321BRMZ1的Datasheet PDF文件第7页浏览型号AD5321BRMZ1的Datasheet PDF文件第8页 
AD5301/AD5311/AD5321  
AC CHARACTERISTICS1  
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.  
Table 2.  
B Version2  
Parameter3  
Min  
Typ  
Max  
Unit  
Conditions/Comments  
Output Voltage Settling Time  
AD5301  
AD5311  
VDD = 5 V  
7
8
8
9
10  
μs  
μs  
μs  
1/4 scale to 3/4 scale change (0x40 to 0xC0)  
1/4 scale to 3/4 scale change (0x100 to 0x300)  
1/4 scale to 3/4 scale change (0x400 to 0xC00)  
AD5321  
Slew Rate  
Major-Code Change Glitch Impulse  
Digital Feedthrough  
0.7  
12  
0.3  
V/μs  
nV-s  
nV-s  
1 LSB change around major carry  
1 See the Terminology section.  
2 Temperature range for the B Version is as follows: –40°C to +105°C.  
3 Guaranteed by design and characterization, not production tested.  
TIMING CHARACTERISTICS1  
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
Limit at TMIN, TMAX  
Parameter2  
(B Version)  
Unit  
Conditions/Comments  
fSCL  
t1  
t2  
t3  
t4  
400  
2.5  
0.ꢀ  
1.3  
0.ꢀ  
100  
0.9  
0
0.ꢀ  
0.ꢀ  
1.3  
300  
0
kHz max  
μs min  
μs min  
μs min  
μs min  
ns min  
μs max  
μs min  
μs min  
μs min  
μs min  
ns max  
ns min  
ns max  
ns max  
ns min  
pF max  
SCL clock frequency  
SCL cycle time  
tHIGH, SCL high time  
tLOW, SCL low time  
tHD,STA, start/repeated start condition hold time  
tSU,DAT, data setup time  
tHD,DAT, data hold time  
t5  
tꢀ  
3
t7  
t8  
t9  
t10  
tSU,STA, setup time for repeated start  
tSU,STO, stop condition setup time  
tBUF, bus free time between a stop condition and a start condition  
tR, rise time of both SCL and SDA when receiving4  
May be CMOS driven  
tF, fall time of SDA when receiving4  
tF, fall time of both SCL and SDA when transmitting4  
t11  
250  
300  
20 + 0.1Cb  
5
Cb  
400  
Capacitive load for each bus line  
1 See Figure 2.  
2 Guaranteed by design and characterization, not production tested.  
3 A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s  
falling edge.  
4 tR and tF measured between 0.3 VDD and 0.7 VDD  
.
5 Cb is the total capacitance of one bus line in picofarads.  
SDA  
t11  
t9  
t3  
t4  
t10  
SCL  
t2  
t5  
t4  
t6  
t1  
t7  
t8  
START  
CONDITION  
REPEATED  
STOP  
CONDITION  
START  
CONDITION  
Figure 2. 2-Wire Serial Interface Timing Diagram  
Rev. B | Page 5 of 24  
 
 
 
 

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